Test method of FPGA chip application circuit

Abstract

The invention relates to a test method of an FPGA (Field Programmable Gate Array) chip application circuit, and belongs to the technical field of circuit design. For two directly connected LUTs (Look Up Tables) in the circuit, if the two LUTs meet a specific condition, a back redundant line can be added to the previous LUT, or a forward redundant line can be added to a posterior LUT under the condition of ensuring the correct logic function of the circuit. The number of test vectors required by a local circuit can be reduced by adding the forward and backward redundant lines, so that the total number of the test vectors required by a whole circuit can be integrally reduced. Meanwhile, the method provided by the invention has the advantages that unknown faults generated during the original circuit test generation can be reduced to a certain degree, and the circuit test generation difficulty is reduced.

Description

technical field [0001] The invention relates to a method for testing an application circuit of a field programmable gate array chip, belonging to the technical field of circuit design. Background technique [0002] A field programmable gate array chip (hereinafter referred to as FPGA) is a digital logic chip that is generally manufactured and whose function is determined during use. During use, the user uses the general design process provided by electronic design automation tools to integrate the designed digital logic The circuit is converted into a specific FPGA configuration file, and the FPGA chip is configured to make it a definite application circuit with specific functions. In circuit design, the configurability of FPGA makes the implementation of the application circuit not unique, and its design process is realized through a general algorithm, so it is relatively easy to modify the circuit implementation according to the required purpose. At the same time, FPGA ap...

AI Technical Summary

Problems solved by technology

However, when considering circuit testability, that is, to reduce the difficulty of circuit test generation and reduce the overhead of the test process, this method cannot achieve ideal results.

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