Test method of FPGA chip application circuit

A test method and gate array technology, applied in the direction of detecting faulty computer hardware, etc., can solve problems such as not being able to achieve ideal results, and achieve the effects of reducing unknown faults, reducing difficulty, and reducing algorithm complexity

Active Publication Date: 2014-11-05
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when considering circuit testability, that is, to reduce the difficulty of circuit test

Method used

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  • Test method of FPGA chip application circuit
  • Test method of FPGA chip application circuit
  • Test method of FPGA chip application circuit

Examples

Experimental program
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Embodiment Construction

[0031] The method for testing an application circuit of a field programmable gate array chip of the present invention performs functional equivalent reconstruction on the LUT unit pair in the FPGA application circuit. When two directly connected LUT units meet certain constraints, by adding local redundant interconnection lines, the number of test vectors required for the local circuit can be reduced, thereby reducing the total test vectors required for the entire circuit as a whole number. The way of adding redundant interconnection lines can be divided into two types: forward redundant interconnection lines and backward redundant interconnection lines. Specifically include the following steps:

[0032] (1) Between the two directly connected look-up table units of the field programmable gate array chip application circuit, add a backward redundant interconnection line, and the adding method is as follows:

[0033] If two directly connected lookup table units meet the follow...

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Abstract

The invention relates to a test method of an FPGA (Field Programmable Gate Array) chip application circuit, and belongs to the technical field of circuit design. For two directly connected LUTs (Look Up Tables) in the circuit, if the two LUTs meet a specific condition, a back redundant line can be added to the previous LUT, or a forward redundant line can be added to a posterior LUT under the condition of ensuring the correct logic function of the circuit. The number of test vectors required by a local circuit can be reduced by adding the forward and backward redundant lines, so that the total number of the test vectors required by a whole circuit can be integrally reduced. Meanwhile, the method provided by the invention has the advantages that unknown faults generated during the original circuit test generation can be reduced to a certain degree, and the circuit test generation difficulty is reduced.

Description

technical field [0001] The invention relates to a method for testing an application circuit of a field programmable gate array chip, belonging to the technical field of circuit design. Background technique [0002] A field programmable gate array chip (hereinafter referred to as FPGA) is a digital logic chip that is generally manufactured and whose function is determined during use. During use, the user uses the general design process provided by electronic design automation tools to integrate the designed digital logic The circuit is converted into a specific FPGA configuration file, and the FPGA chip is configured to make it a definite application circuit with specific functions. In circuit design, the configurability of FPGA makes the implementation of the application circuit not unique, and its design process is realized through a general algorithm, so it is relatively easy to modify the circuit implementation according to the required purpose. At the same time, FPGA ap...

Claims

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Application Information

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IPC IPC(8): G06F11/22
Inventor 张双悦王红杨士元苗巍
Owner TSINGHUA UNIV
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