Asynchronous fault-tolerant network-on-chip router design method

Abstract

The invention discloses an asynchronous fault-tolerant network-on-chip router design method. The method is based on the quasi delay insensitive logic, utilizes a four-phase handshake protocol and a 1-of-4 coding method, and combines fault-tolerant hardware design of a routing computation unit, that is, according to the relative position relationship of current nodes and target nodes and with the path having the least hops being the target, a data packet is routed by passing fault areas. The method in the invention helps to reduce the area and power consumption cost, reduce the average delay, improve the overall performance of the network, has good expandability and fault-tolerant capability, and is suitable for a large-scale globally-asynchronous and locally synchronization system.

Description

technical field [0001] The invention relates to the application technical field of integrated circuit chips, in particular to an asynchronous fault-tolerant on-chip network router design method. Background technique [0002] The network-on-chip design pattern provides scalable on-chip global communication, replacing the traditional shared bus structure. There are currently two implementations, synchronous and asynchronous. Most of the network-on-chip is a synchronous network-on-chip implemented by synchronous circuits, and the communication between nodes is driven by a single or multiple clocks. However, as the scale of the on-chip network increases, a synchronous NoC requires a huge clock tree design, resulting in a large increase in area and power consumption. At the same time, due to the increasing clock speed, it is difficult to guarantee that the clock can reach every unit on the chip at the same time. However, in the Asynchronous Network on Chip (ANoC) implemented b...

AI Technical Summary

Problems solved by technology

2010 A QDI-based ANoC is proposed, which can perform simple adaptive routing and has a low av

Images