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Asynchronous fault-tolerant network-on-chip router design method

An on-chip network and design method technology, applied in data exchange networks, instruments, computing, etc., can solve the problems of low average delay and poor routing ability, and achieve the effects of reducing area overhead, good scalability and fault tolerance

Inactive Publication Date: 2014-09-24
HEFEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

2010 A QDI-based ANoC is proposed, which can perform simple adaptive routing and has a low average delay, but this method has poor routing ability under certain network failure conditions

Method used

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Embodiment Construction

[0036] A method for designing an asynchronous fault-tolerant network-on-chip router, the steps of which are as follows:

[0037] a. According to the performance to be realized, select the basic mode of asynchronous network-on-chip, such as delay model, handshake protocol, and encoding method, and make a good choice of infrastructure in the early stage.

[0038] b. Set the asynchronous network-on-chip data transmission format, first send the data packet to the network through the resource node, and then transmit the data packet to the local resource node of the destination node after reaching the destination.

[0039] c. The asynchronous network-on-chip router architecture is a key component in the asynchronous network-on-chip, which sets the basic components of the router, such as input and output units, and connections between input and output units.

[0040] d. Design an asynchronous network-on-chip fault model. Knowing the fault model, design a routing algorithm for fault tol...

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Abstract

The invention discloses an asynchronous fault-tolerant network-on-chip router design method. The method is based on the quasi delay insensitive logic, utilizes a four-phase handshake protocol and a 1-of-4 coding method, and combines fault-tolerant hardware design of a routing computation unit, that is, according to the relative position relationship of current nodes and target nodes and with the path having the least hops being the target, a data packet is routed by passing fault areas. The method in the invention helps to reduce the area and power consumption cost, reduce the average delay, improve the overall performance of the network, has good expandability and fault-tolerant capability, and is suitable for a large-scale globally-asynchronous and locally synchronization system.

Description

technical field [0001] The invention relates to the application technical field of integrated circuit chips, in particular to an asynchronous fault-tolerant on-chip network router design method. Background technique [0002] The network-on-chip design pattern provides scalable on-chip global communication, replacing the traditional shared bus structure. There are currently two implementations, synchronous and asynchronous. Most of the network-on-chip is a synchronous network-on-chip implemented by synchronous circuits, and the communication between nodes is driven by a single or multiple clocks. However, as the scale of the on-chip network increases, a synchronous NoC requires a huge clock tree design, resulting in a large increase in area and power consumption. At the same time, due to the increasing clock speed, it is difficult to guarantee that the clock can reach every unit on the chip at the same time. However, in the Asynchronous Network on Chip (ANoC) implemented b...

Claims

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Application Information

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IPC IPC(8): H04L12/703G06F15/173H04L45/28
Inventor 欧阳一鸣欧阳小叶梁华国黄正峰高妍妍陈田王悄李建华
Owner HEFEI UNIV OF TECH
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