ESD Protection Structure, Integrated Circuit and Semiconductor Device

Abstract

Implementations are presented herein that include an ESD protection structure. The structure may include a plurality of first doped regions forming first terminals of a plurality of transistors, a plurality of second doped regions forming second terminals of the plurality of transistors, and a third doped region surrounding the plurality of first doped regions and the plurality of second doped regions to form a common third terminal of the plurality of transistors. The plurality of first doped regions and the plurality of second doped regions may be arranged in an alternating pattern such that an ESD discharge current received on any one of the plurality of first doped regions dissipates through at least two of the plurality of second doped regions.

Description

Background technique [0001] Electrostatic discharge (ESD) protection design is a major factor in terms of integrated circuit reliability. In general, ESD is the transfer of electrostatic charge between subjects at different electrostatic potentials or voltages, either caused by direct contact or induced by an electrostatic field. In order to improve the transistor operating speed and the integration density of integrated circuits, the device dimensions of transistors of integrated circuits and the thickness of oxide and insulating layers are continuously reduced. However, it has been found that these highly scaled devices are increasingly susceptible to ESD. Therefore, ESD protection circuits have been added to integrated circuits to protect the integrated circuits from ESD damage. ESD protection circuitry can be implemented around the input, output, and power pads of an integrated circuit to shunt ESD current away from the internal devices of the integrated circuit. Descr...

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Problems solved by technology

However, these highly scaled devices have been found to be increasingly susceptible to ESD

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