Astronavigation FPGA universal refresh circuit based on JTAG interface and achieving method thereof

Abstract

The invention relates to an astronavigation FPGA universal refresh circuit based on a JTAG interface. The refresh circuit is provided with seven input pins and eight output pins, and the input pins and the output pins are connected with pins of a PROM and pins of an FPGA. The SRAM-type FPGA is subjected to backward reading operation through the JTAG interface, the type of the FPGA is determined, and backward read data are checked; if errors happen, a code stream is read from a correct data source, effective parts are intercepted from the code stream, the effective code stream is written into an inner configuration bit of the FPGA again through the JTAG interface, and accordingly refreshing of a configuration memory is completed. Through the refresh circuit, single event upset of the astronavigation FPGA can be timely detected and corrected, functional faults caused by single event upset of the astronavigation FPGA are eliminated, and astronavigation FPGA space application reliability is improved.

Description

technical field [0001] The invention relates to an aerospace FPGA general refresh circuit based on a JTAG interface and an implementation method thereof, in particular for detecting and recovering a space single-event flip fault occurring in an aerospace SRAM FPGA, and belongs to the technical field of integrated circuits. Background technique [0002] The basic structure of SRAM FPGA is as follows: Figure 5 , the main functional modules include: input and output modules (IOB) around the circle, two columns of block memory (Block RAM) on the edge, and internal programmable logic block array (CLB). In addition, there are connections throughout the entire circuit The interconnection resources of each module. The above logic resources and interconnect resources are all controlled by the underlying SRAM configuration bits. A large number of SRAM configuration bits all over the FPGA circuit determine the specific functions of the FPGA circuit, and the set of bit streams of thes...

AI Technical Summary

Problems solved by technology

This effect is the spatial single event flipping effect. The flipping of the configuration bit state may lead to serious functional failures, resulting in internal functional disorder, short circuit, open circuit, etc.

Faults caused by this configuration bit flip are permanent and can only be removed by reloading the bitstream

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