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Method for replacing FPGA IP programs inside SOC by SOC

A program and chip technology, applied in the field of SOC chip replacing its own internal FPGAIP program, to achieve the effect of reducing cost, simplifying system complexity, and flexible and diverse working modes

Inactive Publication Date: 2014-05-21
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Due to the special requirements of the system for the encryption method, different encryption algorithms must be frequently replaced according to different occasions, that is, the FPGA IP program needs to be replaced online at any time, so as to achieve the purpose of replacing the encryption algorithm. It can load the program in the fixed address area of ​​the FLASH memory, so it is necessary to add additional digital logic to control the loading process of the FPGAIP program

Method used

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  • Method for replacing FPGA IP programs inside SOC by SOC
  • Method for replacing FPGA IP programs inside SOC by SOC
  • Method for replacing FPGA IP programs inside SOC by SOC

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Embodiment Construction

[0028] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0029] Such as figure 1 as shown, figure 1 It is a flow chart of the method that the SOC chip provided by the invention replaces its own internal FPGA IP program, and the method may further comprise the steps:

[0030] Step 1: The MCU IP configures the configuration interface of the FPGA IP through its general-purpose IO interface, so that the FPGA IP under normal working conditions enters the program download mode;

[0031] Step 2: MCU IP inputs specific command bytes for reading data to the serial FLASH memory through its general-purpose IO interface, and then inputs the start address where the program code to be configured is located, so that the serial FLASH memory sends FPGA IP from the start address Start outputti...

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Abstract

The invention discloses a method for replacing FPGA IP programs inside an SOC by the SOC. The method includes the steps that MCU IP configures a configuration interface of FPGA IP through a general IO interface of the MCU IP, and then the FPGA IP in a normal working state is in a program downloading mode; the MCU IP inputs specific command bytes of read data to a serial FLASH storage through the general IO interface of the MCU IP, then inputs the initial address where program codes needing configuring are located, and then the serial FLASH storage outputs data to the FPGA IP from the initial address; the FPGA IP in the program downloading mode begins to receive data output by the serial FLASH storage to conduct program downloading; when the FPGA IP receives all the data output by the FLAH storage, program downloading work is completed, the program downloading mode is retreated, a configuration completion mode is executed, and then the FPGA IP programs inside the SOC can be replaced.

Description

technical field [0001] The invention relates to the field of embedded systems, in particular to a method for replacing an internal FPGAIP program of an SOC chip. Background technique [0002] In today's embedded systems, due to the increasing demand for functions and performance, the design complexity of embedded systems also increases, so SOC chips can be seen in almost all embedded systems. [0003] By integrating multiple IP cores required by the system, such as MCU IP, DSP IP, FPGAIP and other IP cores for processing digital signals and IP cores for processing analog signals, it is possible to integrate a lot of individual chip functions in a small chip volume , greatly improving the integration of a single chip, thus simplifying the design complexity of the entire embedded system. [0004] The SOC chip involved in the present invention is a SOC chip that integrates FPGA IP and MCU IP, wherein FPGA IP is an FPGA IP with a capacity of 2000 logic units independently devel...

Claims

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Application Information

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IPC IPC(8): G06F9/445
Inventor 徐飞乔树山黑勇
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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