FPGA testing device and method

Abstract

The invention provides a FPGA testing device and method. The FPGA testing device is disposed in a FPGA chip and comprises a self-testing controller, an address generator, and a data generator. The self-testing controller is used for generating an address generating signal and backward read enabling signal according to a preset time sequence. The address generator is used for generating addresses containing a tested FPGA configuration array under the driving of the address generating signal, and enabling the FPGA configuration array corresponding to the addresses in a corresponding read-write state. The data generator is used for firstly reading configuration data from the FPGA configuration array and converting the configuration data into a set of new testing configuration data according to each address provided by the address generator under the effect of the backward read enabling signal, and then rewriting the newly-generated testing configuration data in the address of the FPGA configuration array. The FPGA testing device and method decrease the times of externally loading testing configuration in series of a chip, increase testing efficiency, and reduce testing cost.

Description

technical field [0001] The present invention relates to field programmable gate array (Field programmable gate array, FPGA for short) design field, particularly relate to a kind of device and method for testing FPGA. Background technique [0002] The generation test of FPGA is generally composed of multiple test sessions (test sessions). A test session FPGA test can be roughly divided into three steps: 1. Loading test configuration; 2. Loading stimulus; 3. Observing test response. The purpose of test configuration loading is to configure it into a specific circuit structure to facilitate testing. The test configuration code is a string of binary codes, the length of which can reach tens of millions to hundreds of millions of bits, and is serially downloaded to the configuration bit array of the FPGA to complete a test configuration load. Subsequently, a test stimulus is applied to obtain a test response. By comparing the obtained test response with the expected test respon...

AI Technical Summary

Problems solved by technology

This type of method is more effective for FPGAs with a relatively regular structure, but with the increasing complexity of the FPGA array, the optimization effect brought by this type of method is greatly affected

[0006] The applicant found that the existing technology has the following technical defects: the overhead caused by the loading test configuration is very large, which affects the test efficiency and increases the test cost

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