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Chip packaging method and structure

A chip packaging structure and chip packaging technology, which is applied to semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of poor reliability of chip packaging methods, and achieve the effect of simplifying the process

Active Publication Date: 2017-11-03
CHINA WAFER LEVEL CSP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The problem solved by the invention is that the reliability of the prior art chip packaging method is poor

Method used

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  • Chip packaging method and structure
  • Chip packaging method and structure

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Embodiment Construction

[0035] Usually, when two chips of different sizes are packaged in a system-in-package, the connection area between the big chip and the small chip is only the size of the small chip. Please refer to figure 1 , figure 1 It is a schematic cross-sectional structure schematic diagram of system-in-package for two chips with different sizes in the prior art, including: a first chip 110, the surface of the first chip 110 has a first pad 111 and a third pad 112; Chip 120, the area of ​​the second chip 120 is smaller than the first chip 110, the surface of the second chip 120 has a second pad 121, the second pad 121 on the surface of the second chip 120 is connected to the The first pads 111 on the surface of the first chip 110 are correspondingly bonded together; the insulating glue 130 is located in the gap between the surface of the first chip 110 and the surface of the second chip 120, and is used to bond the first chip 110 and the second chip 120; solder balls 140, located on th...

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Abstract

A chip packaging method and structure, the chip packaging method comprising: providing a first chip, the surface of the first chip has a plurality of first pads; providing a second chip, the surface of the second chip has a plurality of The second pads, the plurality of second pads correspond to the positions of the plurality of first pads, and the area of ​​the second chip is smaller than the area of ​​the first chip; the second chip A plurality of second pads on the surface are correspondingly combined with a plurality of first pads on the surface of the first chip; a first insulating layer is formed, and the first insulating layer covers the second chip and is in contact with the The first chip is bonded. The chip packaging method of the invention improves the reliability of the packaging structure.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip packaging method and structure. Background technique [0002] With the continuous progress of semiconductor chip manufacturing, integration and packaging technology, electronic systems gradually show the development trend of multi-function, high performance and high reliability. In order to combine multiple active and passive components with different functions, as well as other components such as MEMS and Optics components in the same package, making it a system that can provide multiple functions Or subsystems, the industry has proposed system-in-package technology. [0003] The system-in-package can be used as a standard unit for PCB assembly, or it can be the final electronic product. Different from traditional chip packaging, system-in-package can be applied not only to digital systems, but also to optical communication, sensors, MEMS and other fields. Theref...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L23/498H01L23/488H01L25/16
CPCH01L24/09H01L24/14H01L24/73H01L24/81H01L2224/73204H01L2924/1461H01L2224/16145H01L2224/1703H01L2224/171H01L2924/00
Inventor 李俊杰王之奇杨莹喻琼祁俊华张坚王蔚
Owner CHINA WAFER LEVEL CSP
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