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On-chip network communication deadlock avoidance method, router and communication network

An on-chip communication and network deadlock technology, applied in the field of network communication, to achieve the effect of reducing the probability of multicast deadlock

Active Publication Date: 2019-04-12
XIDIAN UNIV +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention proposes a tree-based on-chip network communication deadlock avoidance method, router and communication network, with the purpose of solving the problem of how to avoid deadlock in tree-based multicast communication using a single virtual channel wormhole switching method

Method used

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  • On-chip network communication deadlock avoidance method, router and communication network
  • On-chip network communication deadlock avoidance method, router and communication network
  • On-chip network communication deadlock avoidance method, router and communication network

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Embodiment Construction

[0027] Hereinafter, the present invention will be further described in detail through specific embodiments in conjunction with the drawings.

[0028] This embodiment uses a 4*4 network topology, please refer to figure 1 . In other embodiments, as long as the network topology of N*M is adopted, where N and M are both positive integers, and there is no size limit between N and M, they can be the same or different, such as 3*8, 7* 5, 11*1, etc. Multicast communication in the network adopts a tree-based approach and uses wormhole switching. Multicast packets are distinguished in the form of labels. The labeling rules are: the router in the lower left corner of the network is the origin, the horizontal to the right is the positive direction of the x-axis, and the vertical upward is the positive direction of the y-axis; the router is based on its communication network Use a unique natural number label for the difference in the middle position, preferably a unique and continuous natur...

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Abstract

The invention discloses an on-chip network communication deadlock avoiding method, a router and a communication network. The probability that multicast deadlock caused in multiple multicast groups in the network is reduced through a network layering method, the multicast groups are sent to two output ports at the most in a single communication subnet, and the probability that the multicast deadlock occurs among the multiple multicast groups is reduced greatly. When the deadlock is formed in the multicast tree establishing process, the multicast groups with the deadlock are cached, transmission paths of the other multicast groups are changed to be in the horizontal direction at the same time, and thus the network is made to restore from the deadlock. The on-chip network communication deadlock avoiding method, the router and the communication network have the advantages that communication efficiency is high, and the router is simple in structure and small in design area.

Description

Technical field [0001] The present invention relates to the technical field of network communication, in particular to a tree-based on-chip network communication deadlock avoidance method, router and communication network. Background technique [0002] With the development of integrated circuit technology, the integration of billions of transistors on silicon has become a reality, and processors have entered the era of multi-core. Multi-core processors integrate multiple intellectual property (IP, Intellectual Property) cores on the same chip to form a system on chip (SoC, System on Chip). Because the bus structure technology is mature and easy to implement, the system-on-chip basically uses the bus structure to achieve communication between IP cores. However, with the increase in the number of IP cores, shortcomings such as low resource utilization of the bus structure, difficult clock synchronization, high power consumption of the clock tree, poor scalability, and poor reusabi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/173
Inventor 郑国海顾华玺朱键王铮付希松
Owner XIDIAN UNIV
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