Sequence generator and design method thereof

Abstract

The invention provides a sequence generator and a design method thereof. The sequence generator and the design method of the sequence generator are applied to the field of integrated circuit design. A clock and converting control module caches a specified sequence through a sequence buffering and generating module and configures starting of a sequence generating access; the specified sequence in the sequence buffering and generating module is controlled, generated and sent by a sequence generating and controlling register; when the specified sequence is transmitted through a sequence selecting and controlling module, a sequence selecting and controlling register controls a selected target sequence and outputs the sequence. The sequence generator and the design method of the sequence generator solve the problem of large difficulties in a test of a high speed serial data transmission channel, the specified transmitted sequence can be fast and effectively controlled and generated in a chip, and the specified initial sequence can be controlled, generated and transmitted in the initialization phase.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a sequence generator and a design method thereof. Background technique [0002] With the rapid development of computer technology and integrated circuit technology, high-performance computer systems have increasingly become the needs of economic and social development, which has brought challenges to the protocol and function design of key chipsets in computer systems. For example, in the QPI interface protocol, the interface circuit is required to be able to send several kinds of sequence data, and to send customized sequence data according to user needs; therefore, this brings huge difficulties to the logic design of on-chip serial data sequence generation: on the one hand , a variety of sequence transmission requirements bring difficulty to the logic design complexity of the chip, and additional sequence generation logic is required; on the other hand, high-speed data ...

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Problems solved by technology

For example, in the QPI interface protocol, the interface circuit is required to be able to send several kinds of sequence data, and to send customized sequence data according to user needs; therefore, this brings huge difficulties to the logic design of on-chip serial data sequence generation: on the one hand , a variety of sequence transmission requirements bring difficulty to the logic design complexity of the chip, and additional sequence generation logic is required; on the other hand, high-speed data transmission and timing requirements require the execution efficiency of the sequence generation module to be extremely high

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