Disorder-storage low-power-consumption high-speed comparator

Abstract

The invention relates to a disorder-storage low-power-consumption high-speed comparator which comprises an input sampling switch, a preamplifier, a coupling capacitor, a secondary preamplifier and an output dynamic latch in sequential connection. Auto-zeroed technology of disorder voltage storage is adopted on the basis of a conventional preamplifier latch comparator, and a novel low-power-consumption high-speed secondary preamplifier structure is realized by utilizing a phase inverter with power and voltage controlled; through average-current control technology, average power consumption is lowered while a high-speed high-gain level is provided. Therefore, comparator input disorder voltage is effectively decreased on the whole, speed of the comparator is greatly increased on the basis of not greatly increasing the power consumption, and designing needs of a high-speed data converter can be met better.

Description

technical field [0001] The invention relates to the technical field of mixed signal integrated circuits, in particular to a low-power high-speed comparator with offset storage. Background technique [0002] With the continuous development of semiconductor process technology, digital systems are more and more commonly used in signal / information processing due to their advantages of high reliability, high integration, and low cost, and more and more traditional analog functions are also used in digital systems. be realized in. But in most cases, the real world provides an analog signal. Therefore, the data converter (A / D, D / A), as the interface between digital signal and analog signal, plays an irreplaceable role in the signal processing system. [0003] The high-speed and high-precision design requirements of the data converter in the application bring challenges to the design of the comparator. There is an inherent offset voltage in the comparator, especially in the compa...

AI Technical Summary

Problems solved by technology

There is an inherent offset voltage in the comparator, especially in the comparator structure with a latch, the CMOS latch has a large offset voltage, sometimes even reaching tens of millivolts, and the offset voltage seriously affects the accuracy of the comparator

The existing pre-amplified latch comparator structure effectively reduces the influence of the offset voltage of the latch by inserting multi-stage pre-amplification gain stages between the latch and the input signal, but introduces the offset voltage of the previous pre-amplification stage

By introducing multi-stage pre-ampli

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