Multilevel gating device

Abstract

The embodiment of the invention provides a multilevel gating device applied in gating of bit lines of a memory array, and is applied in gating of the bit lines of the memory array. The multilevel gating device comprises multilevel gating modules, wherein first level gating modules are connected with continuous bit lines, and the two first level gating modules are connected with each other through shared bit lines; second level gating modules are respectively connected with the first level gating modules, secondary bit lines connected with the second level gating modules are independent to one another, and the second level gating modules reuse second level gating control signal applying terminals to control gating; each two adjacent second level gating modules are connected to one same third level gating module, third level gating control signal applying terminals are used for controlling gating, and each third level gating module is controlled by control signals independent to the other third level gating control modules. The multilevel gating device improves scalability of a gating device.

Description

technical field [0001] The invention relates to the field of memory, in particular to a multilevel gate device applied to memory array bit line gate. Background technique [0002] As the demand for high-density storage arrays increases, storage arrays with virtual land structures are more and more widely used in storage devices. Virtual land structure storage array see figure 1 , the memory cells cell00, cell01...cellMN of the memory array 10 are arranged in an array in the form of M rows and N columns, each memory cell includes a plurality of connection ports, and one of the connection ports is used as a control port to connect to the word line gating device, The two connection ports are respectively connected to a bit line, and the bit line is connected to the bit line gating device 11, and the bit line connection ports of each column of memory cells share the same bit line with the memory cells of adjacent columns, figure 1 The bit line connection port of the memory cel...

AI Technical Summary

Problems solved by technology

figure 1 In the shown bit line gating device, one gating control signal can only gating one bit line. When a (a>2) bit lines need to be gating, each gating control signal corresponds to gating one bit line. The required gating control signal is a, resulting in low gating efficiency of the gating control signal

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