Pipeline Design Method and System for Decoder Motion Compensation Module

Abstract

The present invention provides a pipeline design method of a decoder motion compensation module, which includes four sub-modules: reference data reading, inter-frame interpolation, weighted prediction, and data reconstruction, and at least includes: 1) The inter-frame interpolation module completes reference data reading When fetching, the motion compensation module is divided into 2 pipeline segments: the first pipeline segment and the second pipeline segment; 2) complete the work of reference data reading and inter-frame interpolation data input in the first pipeline segment; 3 ) In the second pipeline segment, the inter-frame interpolation data output, weighted prediction calculation, and data reconstruction work are completed; 4) The first pipeline segment and the second pipeline segment are in parallel working state, and the motion compensation module starts and ends Except the period; adopt the design scheme in the present invention, the number of clock cycles needed to process a bidirectional predictive macroblock is (11+7)*(32+1)=594, corresponding to complete 1080P high-definition real-time decoding, the decoder required by the former The operating frequency is 144.342MHz, and the required operating frequency of the decoder has a 43.75% benefit; in addition, the hardware implementation complexity of the present invention is much lower than that of the 8x8 design scheme, and there is only a very small increase compared to the traditional 4x4 design scheme .

Description

technical field [0001] The present invention relates to a pipeline design of a motion compensation module based on an H.264 decoder, in particular to a method and system for a pipeline design of a motion compensation module of an H.264 decoder based on a 4x4 sub-block as a minimum processing unit. Background technique [0002] The current mainstream H.264 decoder usually adopts a multi-stage pipeline design based on macroblocks. The most common H.264 decoder is usually divided into: entropy decoding module and motion vector generation module, inverse change quantization module and data acquisition module, motion compensation module, intra-frame interpolation module, and deblocking filter module. The above-mentioned motion compensation module mainly completes the functions of reference data selection, inter-frame interpolation, weighted prediction, and data reconstruction. As the module with the largest amount of memory access and calculation in the H.264 decoder, the hardwar...

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Problems solved by technology

[0005] The purpose of the present invention is: in the motion compensation module design scheme using 4x4 sub-blocks as the minimum processing unit, by introducing the pipeline design between 4x4 sub-blocks inside the motion compensation module, on the basis of slightly increasing the complexity of control logic, obtain It achieves a processing speed similar to that of the 8x8 sub-block as the minimum processing unit design, and can meet the requirements of 1080P high-definition real-time decoding at a working frequency of less than 150MHz, and overcomes the traditional 4x4 sub-block design. High-definition decoding operating frequency requirements are too high disadvantages, and the corresponding hardware implementation complexity is much lower than the 8x8 design scheme, compared with the traditional 4x4 design scheme, there is only a very small increase

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