Field programmable gate array chip layout method

Abstract

The invention provides a field programmable gate array chip layout method. The method includes providing structural information of a logic unit of a field programmable gate array chip and net list information, generated after packaging, of a logic module; establishing a wiring resource map according to the structural information of the logic unit of the chip; arranging the field programmable gate array chip according to the net list information and the wiring resource map, and quickly wiring simultaneously. By the method, quick wiring is realized in the overall arrangement process according to the wiring resource map, and overall arrangement and wiring are closely combined, so that wiring success rate is increased, time delay of a circuit is reduced, and wiring resource utilization rate is increased.

Description

technical field [0001] The invention relates to the fields of integrated circuit design and electronic design automation, in particular to a field programmable gate array chip layout method. Background technique [0002] FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) chip is a programmable device widely used in the market at present, and has the advantages of short development period and low cost. Through the layout of logic modules and the wiring of interconnection lines between logic modules, FPGA chips can realize various applications. Therefore, in the software flow of FPGA design, layout and wiring are crucial steps. The layout determines the position of each logic module required to realize the circuit function in the FPGA chip, and the logic modules are connected by the wiring of the interconnection line. The optimization goal of the layout is to place the connected logic modules close to minimize the required At the same time, it is also necessa...

AI Technical Summary

Problems solved by technology

In most layout and routing tool software, the relationship between layout and routing is too loose. Usually, the interconnection lines used in the wiring stage cannot be predicted during layout, so the delay caused by the interconnection lines cannot be predicted, which eventually leads to FPGA chips. Increased delay

[0004] At present, the best solution to reduce the delay of FPGA chips is to perform layout and routing at the same time. However, when the layout and routing are performed at the same time, the running time of the placement and routing tool software will increase by more than ten times, which seriously affects the placement and routing time of the FPGA chip.

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