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Adder

A technology of adder and full adder, which is applied in the field of adder, can solve the problem of long time-consuming and achieve the effect of shortening the time required

Active Publication Date: 2013-09-04
RUIJIE NETWORKS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0026] An embodiment of the present invention provides an adder to solve the time-consuming problem of using a full adder to realize multi-bit binary addition in the prior art

Method used

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Embodiment Construction

[0039] In order to solve the problem in the prior art that using a one-bit full adder to implement multi-bit binary addition takes a long time, an embodiment of the present invention provides an adder. The adder can process multi-bit one-digit numbers in parallel to realize multi-bit binary addition.

[0040] The embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention. And in the case of no conflict, the embodiments in this description and the features in the embodiments can be combined with each other.

[0041] Embodiments of the present invention firstly provide a simple adder, the specific structural diagram of the adder is as follows image 3 As shown, it includes n one-bit full adders (hereinafter referred to as full adders) that are connected in s...

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PUM

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Abstract

The invention discloses an adder and aims to solve the problem that multi-bit binary addition by a 1-bit full adder in the prior art is time-consuming. The adder comprises a plurality of one-bit full adders serially connected according to a first series rule to form a loop. Each full adder comprises a first addend input end, a second addend input end, a carry value input end, a sum output end, and a carry value output end, wherein the sum output end is used for outputting a sum of a first addend and a second addend, and the carry value output end is used for outputting a carry value obtained by adding the first addend and the second addend. The first series rule includes: the carry value output end of one of each two adjacent full adders is connected with the carry value input end of the other full adder.

Description

technical field [0001] The invention relates to the technical field of programmable design, in particular to an adder. Background technique [0002] FPGA is a new high-performance programmable chip with high integration, suitable for high-speed, high-density high-end digital logic circuit design. Because its internal circuit function is programmable (Programmable), it can flexibly implement extremely complex circuit functions inside it through hardware description language (Hardware Description Language, HDL) and special design tools. [0003] In the field of FPGA design, area usually refers to FPGA chip resources, including logic resources and I / O resources. Speed ​​generally refers to the highest frequency at which the FPGA works. Since the smaller the area, it means that the function of the product can be realized at a lower cost. Therefore, in actual design, using the smallest area to design the highest speed is the goal pursued by every developer. [0004] The advant...

Claims

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Application Information

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IPC IPC(8): G06F7/505
Inventor 郭发长
Owner RUIJIE NETWORKS CO LTD
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