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Method for reducing over electroplating on surface of wafer after through silicon via (TSV) is electroplated with copper

A technology of through-silicon vias and electroplating copper, which is applied in the direction of circuits, electrical components, and electrical solid devices, and can solve problems such as copper overplating on the surface of wafers, and achieve the effects of blocking copper deposition, simple process, and cost reduction

Active Publication Date: 2015-07-08
NAT CENT FOR ADVANCED PACKAGING CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, through-silicon via (TSV) vertical interconnection technology has been widely used in the field of microelectronic packaging, and TSV electroplating copper hole filling technology is an indispensable part of the TSV process. The current TSV electroplating and filling technology will inevitably make There is copper overplating on the wafer surface, which causes the chemical mechanical polishing (CMP) process burden, so a new process method is needed to reduce the copper deposition on the wafer surface

Method used

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  • Method for reducing over electroplating on surface of wafer after through silicon via (TSV) is electroplated with copper
  • Method for reducing over electroplating on surface of wafer after through silicon via (TSV) is electroplated with copper

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Effect test

Embodiment 1

[0025] Such as figure 2 As shown, a sample to be plated that reduces the overplating of the wafer surface after copper plating through silicon vias includes a wafer 5, and a vertical through silicon hole 4 is etched on the surface of the wafer 5, from the inside to the surface of the wafer 5. An insulating layer 3 , a diffusion barrier layer 2 and a copper seed layer 1 are sequentially arranged outside; a special layer 6 is also arranged outside the copper seed layer 1 ; the thickness of the special layer 6 is 4-200nm.

[0026] The material of the special layer 6 is metal Ta, V, Ti, Al, Fe or non-metal TiN, TaN, AlN.

[0027] The material of the diffusion barrier layer 2 is one of Ta, Ti, Ni, TaN and TiN.

[0028] The thickness of the special layer 6 is 4-50nm.

[0029] The thicknesses of the diffusion barrier layer 2 and the copper seed layer 1 are both 10-200mm.

[0030] The height of the special layer 6 at the opening of the vertical TSV 4 is not greater than the sum of...

Embodiment 2

[0032] Such as figure 1 As shown, before the vertical through-silicon via TSV electroplating copper filling process in the present invention, a special layer 6 is made on the wafer surface and the vertical through-silicon via 4 orifices, such as figure 2 As shown, its effect is to reduce (compared to copper seed layer 1) or inhibit copper deposition of copper on the wafer surface. Specific steps are as follows:

[0033] (1) Through-hole etching: take the wafer 5, and etch vertical through-silicon holes 4 on its surface through deep reactive ion etching equipment;

[0034] (2) Preparation of the insulating layer: take the wafer 5 after the etching in step (1), and use silicon dioxide or silicon nitride to prepare the insulating layer 3 by plasma-enhanced chemical vapor deposition; a liquid reaction source is selected, The deposition temperature is 400°C, and the deposition thickness is 10nm;

[0035] (3) Preparation of the diffusion barrier layer and the copper seed layer: ...

Embodiment 3

[0040] (1) Through-hole etching: take the wafer 5, and etch vertical through-silicon holes 4 on its surface through deep reactive ion etching equipment;

[0041] (2) Preparation of the insulating layer: take the wafer 5 after the etching in step (1), and use silicon dioxide or silicon nitride to prepare the insulating layer 3 by plasma-enhanced chemical vapor deposition; a liquid reaction source is selected, The deposition temperature is 400°C, and the deposition thickness is 300nm;

[0042] (3) Preparation of the diffusion barrier layer and the copper seed layer: take the wafer 5 prepared in step (2), and deposit the diffusion barrier layer 2 on the outside of the insulating layer 3 by physical vapor deposition at a deposition temperature of 220°C; A layer of copper seed layer 1 is deposited on the outer side of the barrier layer (2) again by physical vapor deposition, and the deposition temperature is 500°C;

[0043] (4) Preparation of the special layer: take the wafer 5 ob...

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Abstract

The invention relates to a method for reducing over electroplating on the surface of a wafer after a through silicon via (TSV) is electroplated with copper, and belongs to the technical field of wafer-level electro-coppering pore filling. According to the method, after the TSV is vertically etched and an insulation layer, a copper diffusion barrier layer and a copper seed layer are formed on the surface of the wafer in sequence, a special layer is further formed on the surface of the wafer and in the position of a port of the vertical TSV before an electroplating copper-filling process, the special layer is made of metal Ta, V, Ti, Al and Fe or non-metal TiN, TaN and AlN, and the height of the special layer in the port position of the vertical TSV is not larger than the sum of the thicknesses of the insulation layer, the copper diffusion barrier layer and the copper seed layer on the surface of the wafer. The method for reducing over electroplating on the surface of the wafer after the TSV is electroplated with copper is simple in process, is capable of effectively preventing copper from being deposited on the surface, relieves the burden of chemical mechanical polishing (CMP), and lowers the cost.

Description

technical field [0001] The invention relates to a method for reducing over-plating on the surface of a wafer after electroplating copper in through-silicon holes, and belongs to the technical field of wafer-level electroplating copper hole filling. Background technique [0002] At present, through-silicon via (TSV) vertical interconnection technology has been widely used in the field of microelectronic packaging, and TSV electroplating copper hole filling technology is an indispensable part of the TSV process. The current TSV electroplating and filling technology will inevitably make There is copper overplating on the wafer surface, which causes the chemical mechanical polishing (CMP) process burden, so a new process method is needed to reduce the copper deposition on the wafer surface. Contents of the invention [0003] The purpose of the present invention is to overcome the deficiencies of the prior art, and propose a method for reducing the over-plating on the surface o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/538H01L21/768
Inventor 于大全伍恒程万
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD
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