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Successive approximation register analog to digital converter

An analog-to-digital converter and successive approximation technology, applied in analog/digital conversion, code conversion, instruments, etc.

Inactive Publication Date: 2013-07-31
NXP BV
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  • Abstract
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Problems solved by technology

As a result, additional settling time may be introduced

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  • Successive approximation register analog to digital converter
  • Successive approximation register analog to digital converter
  • Successive approximation register analog to digital converter

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[0032] While the present disclosure can be modified into various modifications and alternative forms, details thereof have been shown by way of example in the drawings and examples will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure including aspects defined in the claims.

[0033] One or more embodiments provide a SAR ADC circuit employing a non-binary search algorithm that can be implemented in the digital domain. A non-binary lookup algorithm can help eliminate settling error requirements for resistive DAC outputs, improve immunity to reference and supply noise, and digitally correct for comparator metastability.

[0034] In one embodiment, an N-bit SAR ADC includes a comparator, a binary-weighted resistive DAC, and a digital contro...

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Abstract

An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

Description

technical field [0001] The present invention relates to successive approximation register analog-to-digital converters and methods for digital-to-analog conversion. Background technique [0002] Several analog-to-digital converter (ADC) methods are implemented using successive approximation. In successive approximation, a binary search algorithm is employed, where the analog voltage is compared to a reference voltage during a large number of cycles. In each cycle, the analog voltage is compared to a reference voltage to determine the digital bit value. If the input voltage is greater than the reference voltage, a step voltage is added to the current reference voltage. The newly generated voltage is used as a reference voltage input for the next cycle stage for a more accurate comparison. In each successive cycle of the binary search, the search space is roughly halved by adjusting the reference voltage to be centered within the remaining possible voltage range. In this w...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/38
CPCH03M1/46H03M1/144H03M1/069
Inventor 吴琼凯文·马胡提胡庆海
Owner NXP BV
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