Semiconductor device and method for accelerating erasure verification procedure

Abstract

The invention discloses a semiconductor device and a method for accelerating an erase verification procedure by the same. An erase verification correction unit is connected between a damaged bit line in the semiconductor device and a page buffer; through a special line arrangement on the damaged bit line, a grounding switch of the erase verification correction unit can connect the damaged bit line to a grounding voltage during an erase verification procedure, so that the page buffer can receive the grounding voltage to further verify that the damaged bit line has passed the erase verification, thereby substantially saving repeated verification time consumed in the prior art.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of accelerating an erase verification procedure. Background technique [0002] In flash memory devices, a verify operation is necessary to confirm that the charge is properly injected into the memory cell by the programming operation. If the verification operation fails, the programmed operation and the verification operation will be repeated until the result of the verification operation is successful or a special condition is met (for example, when repeated 100 times and still fails). [0003] In an erase operation, a verify operation is similarly performed to confirm that charge is properly removed from the memory cell. Erase verification usually precharges the bit line to a voltage level, the erased memory cell will discharge the bit line, and the page buffer connected to the bottom of the bit line will verify whether the bit line is di...

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Problems solved by technology

[0004] However, once the bit line of the memory cell is damaged or disconnected due to process defects or other failures, although the memory cell with the damaged bit line will be replaced by a redundant memory cell, the erase verification command ERV is still valid. The verification process will be performed on the damaged bit line, and the verification process will be stopped after a certain period of repeated failures, resulting in an excessively long erase verification time

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