Implementation method of floating point multiply-accumulate unit low in power consumption and high in huff and puff

Abstract

The invention discloses an implementation method of floating point multiply-accumulate unit low in power consumption and high in huff and puff. The implementation method of the floating point multiply-accumulate unit low in power consumption and high in huff and puff comprises the following steps: 1, when a vector point multiplication operation is calculated, a pair of operating number A and operating number B are input in each period from N periods, and a floating-point multiplication operation of the operating number A and the operating number B is operated by a first level production line, a second level production line and a third level production line; 2, product is transformed in a weight mode in a fourth level production line, mantissa bit width is increased, and index number bit width is reduced; 3, accumulation operation is conducted on the transformed product in a fifth level production line, the product is accumulated for one time in each period; 4, recovering of the product is conducted by a sixth level production line and a seventh level production line, and an eventual accumulated result is output at a N plus 6 period. The implementation method of the floating point multiply-accumulate unit low in power consumption and high in huff and puff can complete the vector point multiplication operation of random length N, multiple accumulation is calculated for one time in each period, thereby avoiding frequent access operation of a register of a processor. The operation can be completed with N plus 6 periods, single precision and double precision floating point number are compatible, and power consumption of floating point operation is effectively reduced.

Description

technical field [0001] The invention relates to the design field of a central processing unit and a core operation unit in a digital signal processor, in particular to a method for realizing a floating-point multiplication and accumulation unit with low power consumption and high throughput. Background technique [0002] The rapid development of computer and communication technology has greatly changed our work and lifestyle. Human production and life are increasingly dependent on computers and other equipment. Scientific research and engineering applications have put forward high requirements for the performance of floating-point numbers. , where multiply-accumulate is the key operation unit in digital signal processing and scientific calculation. [0003] In the traditional structure, due to the data correlation of the vector dot multiplication operation, the pipeline cannot calculate the multiplication and accumulation once per cycle, so the throughput rate will drop sign...

AI Technical Summary

Problems solved by technology

[0003] In the traditional structure, due to data correlation, the pipeline cannot calculate the multiplication and accumulation once per cycle, so the throughput rate will drop significantly, and the number of floating-point operations per second is far from the peak performance.

When implementing such as a finite-length unit impulse response filter, the traditional floating-point arithmetic device needs multiple register access operations to complete, and the performance loss is serious

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