Synthesizable pseudorandom verification method and device for high-speed buffer memory

Abstract

The invention discloses a synthesizable pseudorandom verification method and device for a high-speed buffer memory. The method comprises the following steps: (1) setting and initializing a data mirroring module; and (2) generating pseudorandom numbers, structuring a fetching control data signal, sending the fetching control data signal to the high-speed buffer memory, meanwhile, starting an overtime counter, and reporting an overtime error in case of a timeout; and when receiving read data and read identification (ID) numbers, which are returned by the high-speed buffer memory, comparing the returned read data with the data mirroring module, judging whether the access of the high-speed buffer memory fails or not, and meanwhile, judging whether an ID is mistakenly read and an error correcting code is mistakenly checked. The device comprises a data mirroring module, a pseudorandom number generator, a restriction, guidance, testing, excitation and generation module and an automatic error checking module. The synthesizable pseudorandom verification method and device have the advantages of high verification efficiency, high verification coverage and good verification quality.

Description

technical field [0001] The invention relates to the field of cache memory (Cache), in particular to a cache-oriented synthesizable pseudo-random verification method and device. Background technique [0002] With the rapid development of ultra-deep submicron and VLSI (Very Large Scale Integration, VLSI) design technology, the feature size of the process is getting smaller and smaller, the scale of the chip is getting larger and more complex, and the design The cycle is getting longer and longer, and a lot of time is spent on the functional verification of the chip. [0003] The so-called functional verification means that no matter whether it is behavior level, register transition level (RTL) level or gate level circuit, it must meet the system specification, and its purpose is to find errors in the chip logic design. The general view in the industry is that functional verification has already accounted for about 70% of the entire chip design cycle. Formal verification, sof...

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Problems solved by technology

Formal verification can achieve 100% coverage, but there is a problem of state explosion, which leads to a limited design scale; although the software simulation verification method is easy to check for errors, due to its slow speed, when the design scale reaches millions of gates or even several When the gate level is tens of millions, the simulation runtime is expensive and it is difficult to achieve high coverage

The most commonly used in hardware simulation verification is the simulation based on FPGA (Field Programmable Gate Array). Difficult, test stimuli must be synthesizable

[0024] The above methods all use the pseudo-random method to verify the design, but the above methods are based on software simulation technology, which has the advantage of being easy to check for errors and easy to analyze coverage, but its disadvantage is that it runs slowly and takes a lot of time. The efficiency and coverage of verification are limited, and it is difficult to bridge the gap between the huge verification space and verification capabilities, and cannot meet the verification requirements of cache memory chips with increasing scale

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