Manufacturing method of array substrate, array substrate and display device

Abstract

A method for fabricating an array substrate, an array substrate and a display device are provided. The method for fabricating the array substrate includes: forming a spacer layer on the array substrate, the spacer layer is disposed under a planarized layer and corresponds to a location of a via hole in the planarized layer, wherein the planarized layer is formed of a hot melt material.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a manufacturing method of an array substrate, an array substrate and a display device. Background technique [0002] In the manufacturing process of the array substrate, a planarization layer is usually formed before the formation of the pixel electrodes to reduce the level difference on the substrate, making the formation of the pixel electrodes easier and reducing defects. The parasitic capacitance formed between them, the planarization layer is generally made into a thicker layer. However, when making the via holes on the planarization layer, such as the via holes connecting the pixel electrode and the TFT drain electrode, or the via holes in the binding area of ​​the driving circuit, etc., it is necessary to expose the planarization layer. The layer is relatively thick, in order to obtain the expected size of the via hole, a higher exposure energy is required, which...

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Problems solved by technology

However, when making the via holes on the planarization layer, such as the via holes connecting the pixel electrode and the TFT drain electrode, or the via holes in the binding area of ​​the driving circuit, etc., it is necessary to expose the planarization layer. The layer is relatively thick. In order to obtain the expected via hole size, higher exposure energy is required, which reduces the exposure speed and affects production efficiency.

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