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Detection of word-line leakage in memory arrays: current based approach

A memory circuit and memory technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as endangering memory operation

Inactive Publication Date: 2013-04-24
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, both types of defects can compromise memory operations if left undetected

Method used

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  • Detection of word-line leakage in memory arrays: current based approach
  • Detection of word-line leakage in memory arrays: current based approach
  • Detection of word-line leakage in memory arrays: current based approach

Examples

Experimental program
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Embodiment Construction

[0048] memory system

[0049] Figure 1 to Figure 11 An example memory system is illustrated in which various aspects of the invention may be implemented.

[0050] figure 1 Functional blocks of a nonvolatile memory chip in which the present invention can be implemented are schematically illustrated. The memory chip 100 includes a two-dimensional array 200 of memory cells, a control circuit 210 and peripheral circuits such as decoders, read / write circuits and multiplexers.

[0051] Memory array 200 is addressable by word lines via row decoders 230 (separated as 230A, 230B) and by bit lines via column decoders 260 (separated as 260A, 260B) (see also Figure 4 and 5). Read / write circuitry 270 (separately 270A, 270B) allows a page of memory cells to be read or programmed in parallel. Data I / O bus 231 is coupled to read / write circuitry 270 .

[0052] In a preferred embodiment, a page is made up of consecutive rows of memory cells sharing the same word line. In another embo...

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Abstract

Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.

Description

technical field [0001] The present invention relates generally to semiconductor memory circuits, such as Electrically Erasable Programmable Read Only Memory (EEPROM) and flash EEPROM, and in particular, to the detection of defective word lines in such memory circuits. Background technique [0002] Solid state memory capable of non-volatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as small form factor cards, has recently become the storage of choice in a variety of mobile and handheld devices, especially information appliances and consumer electronics . Unlike RAM (Random Access Memory), which is also solid-state memory, flash memory is non-volatile and retains its stored data even after power is cut off. Although more costly, flash memory is being used more in mass storage applications. Traditional mass storage devices based on rotating magnetic media such as hard drives and floppy disks are not suitable for mobile and handheld enviro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/02
CPCG11C16/04G11C29/025G11C2029/5006G11C29/028G11C29/02G11C29/04G11C16/06
Inventor 李艳D.李J.H.海恩潘锋V.波普里M.卡扎尼加
Owner SANDISK TECH LLC
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