Shift register and array substrate grid driving device
A shift register, gate connection technology, applied in static memory, digital memory information, instruments, etc., can solve problems such as poor stability, the OUTPUT terminal of the output terminal cannot work stably for a long time, and the noise at the output terminal cannot be completely solved.
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Embodiment 1
[0056] See attached figure 2 , Embodiment 2 of the present invention provides a shift register, including:
[0057] The input module 101, in response to the input signal INPUT, is used to provide the input signal voltage INPUT to the pull-up node PU point, wherein the pull-up node is the output node of the input module; including:
[0058] The source and gate of the first thin film transistor M1 are connected to the input signal terminal, and the drain is used as the output node of the input module, that is, as the pull-up node PU point;
[0059] The pull-up module 102 is used for storing the input signal voltage INPUT and providing the first clock signal voltage CLK to the output terminal OUTPUT in response to the pull-up node PU point; including:
[0060] The drain of the second thin film transistor M2 is connected to the first clock signal terminal CLK, the gate is connected to the pull-up node PU, and the source is connected to the output terminal OUTPUT;
[0061] Capac...
Embodiment 2
[0082] see Figure 4 , a shift register provided by Embodiment 2 of the present invention, comprising:
[0083] The input module 101, in response to the input signal INPUT, is used to provide the input signal voltage INPUT to the pull-up node PU point, wherein the pull-up node is the output node of the input module; including:
[0084] The source and gate of the first thin film transistor M1 are connected to the input signal terminal, and the drain is used as the output node of the input module, that is, as the pull-up node PU point;
[0085] The pull-up module 102 is used for storing the input signal voltage INPUT and providing the first clock signal voltage CLK to the output terminal OUTPUT in response to the pull-up node PU point; including:
[0086] The drain of the second thin film transistor M2 is connected to the first clock signal terminal CLK, the gate is connected to the pull-up node PU, and the source is connected to the output terminal OUTPUT;
[0087] Capacitor ...
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