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Copper electroplating composition and method of filling cavities in semiconductor substrates using same

A composition and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc.

Active Publication Date: 2015-12-02
ALCHIMER SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0040] Therefore, the object of the present invention is to solve the problem of filling "via" type structures with copper by means of a solution that is not chemically aggressive towards the seed and barrier layers and does not generate significant amounts of pollutants, especially carbon, chlorine and sulfur. the problem that the "via" type structures are especially used in 3D integrated circuit production

Method used

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  • Copper electroplating composition and method of filling cavities in semiconductor substrates using same
  • Copper electroplating composition and method of filling cavities in semiconductor substrates using same
  • Copper electroplating composition and method of filling cavities in semiconductor substrates using same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0110] Example 1: Partial filling of holes with copper on a tantalum based barrier layer on which a copper seed layer has been deposited using an ethylenediamine-copper complex based composition according to the invention

[0111] A. Materials and equipment

[0112] Substrate:

[0113] The substrate used in this example was made of a 750 μm thick, 4 cm x 4 cm silicon wafer etched with a “through-hole” type cylindrical pattern with a depth of 25 μm and a diameter of 5 μm.

[0114] These patterns are covered with a 400nm thick layer of silicon dioxide, itself coated with a tantalum-based layer deposited by sputtering PVD (Physical Vapor Deposition), which is divided into two sublayers: the tantalum nitride sublayer layer (15nm) and tantalum sublayer (10nm).

[0115] This TaN / Ta "double layer" forms a copper diffusion barrier, such as is used in so-called "via" structures in integrated circuit fabrication.

[0116] A conformal copper seed layer with a thickness of about 200 nm...

Embodiment 2

[0149] Example 2: Partial filling of holes with copper on a tantalum based barrier layer on which a copper seed layer has been deposited using an ethylenediamine-copper complex based composition according to the invention

[0150] A. Materials and equipment

[0151] Substrate:

[0152] The substrate used in this example is the same as that in Example 1.

[0153] Fill solution:

[0154] The solution used in this example is the same as that in Example 1.

[0155] equipment:

[0156] An electrowinning apparatus similar to fountain cells used in the microelectronics industry was used in this example.

[0157] An electrowinning cell contains an anode, which can be made of an inert metal such as platinum-coated titanium, or the same metal as the metal being deposited (copper in this case). A silicon wafer coated with a TaN / Ta barrier layer, itself coated with a copper seed layer, formed the cathode of the deposition cell.

[0158] This two-electrode system was powered using a ...

Embodiment 4

[0189] Example 4: Pore filling with copper on a nickel-based (NiB) barrier layer using an ethylenediamine-copper complex based composition according to the invention

[0190] A. Materials and equipment

[0191] Substrate:

[0192] The substrate used in this example consisted of a 750 μm thick, 4 cm x 4 cm doped (p-type) silicon wafer etched with “through hole” type cylindrical patterns of three different sizes:

[0193] - 25 μm in depth and 7 μm in diameter;

[0194] - 27 μm in depth and 9 μm in diameter; and

[0195] - 28 μm in depth and 11 μm in diameter.

[0196] Using the method described in document WO2010 / 001054, a 50 nm thick conformal NiB layer was deposited on the substrate surface, which layer formed a barrier to copper diffusion.

[0197] Fill solution:

[0198] The solution used in this example is the same as that in Example 1.

[0199] equipment:

[0200] The equipment used in this example is the same as that in Example 2.

[0201] B. Experimental method ...

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Abstract

The subject-matter of the present invention is a composition especially intended for filling, by the electroplating of copper, a cavity in a semiconductor substrate such as a "through-via" structure for the production of interconnects in three-dimensional integrated circuits. According to the invention, this composition comprises in solution in a solvent: copper ions in a concentration lying between 45 and 1500 mM; a complexing agent for the copper consisting of at least one compound chosen from aliphatic polyamines having 2 to 4 amino groups, preferably ethylenediamine, in a concentration lying between 45 and 3000 mM; the molar ratio between the copper and said complexing agent lying between 0.1 and 5; thiodiglycolic acid in a concentration lying between 1 and 500 mg / l; and optionally a buffer system, in particular ammonium sulfate, in a concentration lying between 0.1 and 3M.

Description

technical field [0001] Generally, the present invention relates to electroplating compositions for filling cavities, such as "via" structures, in semiconductor substrates with copper. Background technique [0002] The invention is mainly used in the field of microelectronics for the metallization of through-holes (also known as through-silicon vias, through-wafer vias, or through-wafer interconnects) that are used in electronic chips or chips. Block three-dimensional integration or the key technology of vertical integration. The invention can also be used in other fields of electronics where vias or cavities in the substrate must be filled with copper. In this context, reference is made to the manufacture of interconnected elements in printed circuits (also known as printed circuit boards or printed wiring boards), or passive elements in integrated circuits or microsystems (microelectromechanical systems or MEMS) ( such as inductors) or the manufacture of electromechanical...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): C25D3/38C25D7/12H01L21/288H01L21/768
CPCC25D3/38C25D7/123H01L21/76898H01L21/2885H01L21/02
Inventor 纳迪亚·弗雷德里克弗雷德里克·雷纳尔乔斯·冈萨雷斯
Owner ALCHIMER SA
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