B4-flash device and manufacture method thereof

Abstract

The invention provides a B4-flash device and a manufacture method thereof. The B4-flash device comprises a substrate, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, wherein the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer are sequentially installed on the substrate, the first silicon oxide layer comprises a first section, a second section and a third section which are sequentially distributed along a channel direction, and the thickness ratio of the first section, the second section and the third section is 1.5-2.5:0.8-1.2:1.5-2.5. An embodiment of the B4-flash device remits degeneration of silicon oxide and influences of electronic local area injection compiling and hole uniformity injection wiping through a heterogeneous silicon oxide structure so as to increase reliability of the device.

Description

technical field [0001] The invention relates to a device and a manufacturing method thereof, in particular to a device suitable for B4-flash compilation and hole tunneling injection and erasing and a manufacturing method thereof. Background technique [0002] For NOR flash memory cells, the most important limit to the continued reduction in size is the shortening of the gate length. This is mainly because the channel thermal electron (CHE) injection compilation method requires a certain voltage at the drain terminal, and this voltage has a great influence on the penetration of the source and drain terminals. For short channel devices, the channel thermal electron (CHE) method Not applicable. Another problem is that this limits the compilation yield of NOR flash compared to NAND and AND data storage devices. [0003] Recently, Shoji Shukuri et .al proposed a novel P-channel memory cell ("60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunnel...

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Problems solved by technology

Although this substrate-bias-assisted band-to-band p-channel device has also been reported before, however, in order to obtain enough hot electrons to compile, a high drain voltage is still required, and an excessive drain voltage will make Channel penetration is easy, which limits the gate length (T.Ohnakado, et al., IEEE Trans. EL, Vol.46, No.9, 1999, pp.1866-1870.), which also limits the size of the device reduce

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