Semiconductor package

Abstract

A semiconductor package comprises a packaging substrate; a plurality of semiconductor chips stacked on the packaging substrate in a stagger manner, forming an accommodation space between the packaging substrate and the stacked semiconductor chips; and a control chip integrated with the packaging substrate by flip chip technology and positioned in the accommodation space. As the control chip is arranged in the accommodation space, the thickness of the whole package is reduced so as to achieve the purpose of thinning.

Description

technical field [0001] The invention relates to a semiconductor package, especially a semiconductor package with a control chip. Background technique [0002] The common multi-chip packaging structure adopts side-by-side, so that multiple chips are arranged side by side on the crystal surface of a substrate, and the electrical connection between these chips and the conductive lines on the substrate Generally, it is wire bonding. However, since the area of ​​the substrate increases with the number of chips, the disadvantages of the side-by-side multi-chip package structure are that the package cost is too high and the size of the package structure is too large. [0003] In order to solve the above problems, in recent years, the number of chips has been increased by using a vertical stacking method, and the stacking methods are different according to the chip design and the wire bonding process. For example: the flash memory chip (flash memory chip) or the dynamic random acc...

AI Technical Summary

Problems solved by technology

[0005] However, compared with the side-by-side multi-chip packaging structure, although the above-mentioned semiconductor package can reduce the use area of ​​the packaging substrate 10, it will increase the thickness of the overall package volume, so it is difficult to comply with thinning. needs

[0006] In addition, the control chip 12 is electrically connected to the package substrate 10 by wire bonding, so that the solder pads 120 can only be arranged on the edge of the control chip 12, thereby reducing the number of electrical contacts, resulting in the performance of the control chip 12. upgrade, so that it cannot meet the high performance requirements required by today's end products

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