Diode neutral point clamped three-level inverter current limiting control method and related circuit thereof

Abstract

The invention discloses a diode neutral point clamped three-level inverter current limiting control method and a related circuit thereof. The diode neutral point clamped three-level inverter current limiting control method comprises specific steps as follows: when the current in switching tubes is lowered to be not bigger than a first current preset value, the related circuit drives one of the switching tubes at the inner side of a bridge arm to be switched on; after a first delay time, another one of the switching tubes at the inner side is driven to be switched on; after a second delay time, one of the switching tubes at the inner side is controlled to be switched off, and another one of the switching tubes is controlled to be normally switched on; and all the switching tubes are controlled to be switched on or switched off according to the control time sequence of the diode neutral point clamped three-level inversion circuit. In such control mode, the switching sequence of the switching tubes in the diode neutral point clamped three-level inversion circuit can be controlled, thereby reducing the voltage stress of the switching tubes and ensuring that the voltage stress of the switching tubes can not exceed the standard even if the limited current is exceeded.

Description

technical field [0001] The present application relates to the technical field of inverter current limiting, in particular to a current limiting control method and related circuits of a diode mid-point clamped three-level inverter. Background technique [0002] The inverter is used to convert DC power into AC power, and its circuit mainly includes an inverter bridge, a control logic circuit and a filter circuit. [0003] See figure 1 , shows a schematic diagram of the main circuit of a typical diode neutral-point clamped three-level inverter, which mainly includes four switching tubes: the first switching tube Q1, the second switching tube Q2, and the third switching tube Q3 , the fourth switch tube Q4, and diodes D5 and D6, and each switch tube has diodes connected in antiparallel at both ends, as figure 1 The diodes D1, D2, D3, and D4 are shown; among them, the four switching tubes are controlled by four driving signals to turn on and off, and the switching tubes Q1 and Q...

AI Technical Summary

Problems solved by technology

When the current is limited, the two inner switch tubes (hereinafter referred to as the inner tube) Q2 and Q3 are switched from the off state to the on state at the same time. At this time, the outer switch tube (hereinafter referred to as the outer tube) Q1 or Q4 will bear double The sum of the bus voltage and the additional voltage generated by the parasitic parameters of the line can easily cause a large voltage stress on the outer tube and lead to failure

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