Memory output circuit

Abstract

The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node.

Description

technical field [0001] The present invention relates to memory, and in particular to memory output circuits. Background technique [0002] figure 1 is a block diagram of at least a portion of a conventional memory circuit 100 . The memory circuit 100 includes a memory cell array 120 and a memory output circuit 110 . The memory cell array 120 includes a plurality of memory cells 121˜12n. The storage units 121˜12n are read-only memory (ROM) units and are coupled between a bit line and a bit bar line. Each memory cell 121˜12n includes two NMOS transistors and is coupled to a word line. For example, the memory cell 121 is coupled to the word line WL 1 and includes two NMOS transistors 121a and 121b, and the memory cell 122 is coupled to the word line WL 2 And includes two NMOS transistors 122a and 122b. The gates of the two NMOS transistors of the memory cells 121-12n are coupled to corresponding word lines, and the sources of the two NMOS transistors of the memory cells ...

AI Technical Summary

Problems solved by technology

Therefore, it takes more time to pull up the selection signal Y1 to a high voltage, so that the output time of the stored data is delayed, and the operation speed of the storage output circuit 100 is reduced.

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