Clock gating circuit used for double-edge trigger

Abstract

The invention discloses a clock gating circuit used for a double-edge trigger. The clock gating circuit is a logic unit, wherein the logic unit has four input ends and two output ends including a first input end, a second input end, a third input end, a fourth input end, a first output end and a second output end, wherein the first input end is connected with the first output end, the second input end is connected with the second output end, the third input end is used for receiving an enable signal, the fourth input end is used for receiving a clock signal, the first output end is used for outputting and receiving a clock control signal of the double-edge trigger of a clock gating; and the second output end is used for outputting a inversion signal from the first output end. On a rising edge and a descending edge of the clock signal, when the enable signal is in low level, the first output end is used for copying the first input end; and on the rising edge and the descending edge of the clock signal, when the enable signal is in high level, the first output end is used for copying the second output end. The clock gating circuit can be directly applied in the design of a digital circuit containing the double-edge trigger and is normal in function, thereby effectively solving the problems of burrs and circuit function errors of the traditional clock gating unit.

Description

technical field [0001] The present application relates to a clock gating circuit, in particular to a clock gating circuit suitable for double-edge triggers. Background technique [0002] The power consumption of digital circuits is composed of two parts, one is static power consumption, which is usually expressed as the leakage current of electronic circuits, and the control of this part of power consumption mainly depends on the production process and materials used; the other is dynamic power consumption, which affects the There are many factors for partial power consumption, such as the way the circuit is designed, the complexity of the circuit, and the operating clock frequency. [0003] In digital circuits, the clock signal is often the signal with the largest fanout and the widest distribution in the system. If no control is added, the clock signal will always flip regardless of whether the input signal changes, causing unnecessary power loss. In a typical digital ci...

AI Technical Summary

Problems solved by technology

When using the latch 40 and the AND gate 30 to gate the clock control signal gclk of the double-edge D flip-flop 50, although it overcomes the problem caused by the enable signal en being in the high level state or the low level state of the clock signal clk The glitch phenomenon of the clock control signal gclk caused by instability, but the extra falling edge of the clock control signal gclk will still cause the circuit function error of the double-edge D flip-flop 50

[0015] It can be seen that for the double-edge trigger circuit, the traditional clock gating circuit can no longer realize the original design intention.

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