A method of high-speed interconnection between fpga boards based on aurora protocol

Abstract

The invention provides an aurora protocol based design method for conducting high-speed interconnection between field programmable gate arrays (FPGAs). A data processing and transmission process includes that an optical-fiber signal which comes from another card firstly enters a quad small form-factor pluggable (QSFP) module, and data are extracted according to the aurora protocol in an FPGA. The specific data processing process includes that an electric signal enters a packed-memory array (PMA) of the FPGA, parallel-to-serial conversion of the data is performed in the PMA, data recovery and clock recovery are performed, then a data stream enters a process control system (PCS), block synchronization is performed in the PCS, descrambling, compensation and finally decoding are conducted, and the data stream is delivered to an FPGA logic unit for usage and is delivered to a data center. The data transmission process is an inverse process of data acceptation, data which come from FPGA internal logic are processed by using the Aurora protocol, and the processing process includes that the data enter the PCS, are subjected to coding, scrambling and the like, enter the PMA after completion, and are subjected to serial-to-parallel conversion, sent to the QSFP, subjected to photovoltaic conversion and accepted by another terminal.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a method for high-speed interconnection between FPGA boards based on the aurora protocol. Background technique [0002] In large-scale ASIC verification, often a field programmable gate array FPGA has limited resources, and it is difficult to complete the verification work. Multiple FPGAs need to work together. To work together, multiple FPGAs need real-time communication. A large number of The influx of data has brought great challenges to communication. In the traditional solution, LVDS is used for interconnection between field programmable gate array FPGAs. Although the physical layer of this solution is easier to implement, the rate is limited, PCB wiring is difficult, and the scalability is poor. This design uses optical fiber for serial transmission, and uses the aurora protocol as the transmission protocol, which can easily solve the communication problem of high-speed ...

AI Technical Summary

Problems solved by technology

[0002] In large-scale ASIC verification, often a field programmable gate array FPGA has limited resources, and it is difficult to complete the verification work. Multiple FPGAs need to work together. To work together, multiple FPGAs need real-time communication. A large number of The influx of data has brought great challenges to communication

In the traditional solution, LVDS is used for interconnection between field programmable gate array FPGAs. Although the physical layer is easier to implement in this solution, the rate is limited, PCB wiring is difficult, and the scalability is poor.

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