Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Software-hardware co-verification platform

A software-hardware collaboration and verification platform technology, applied in the detection of faulty computer hardware, functional testing, etc., can solve the problems of limited capacity, high cost, and lengthy hardware debugging cycle, so as to accelerate the development process, avoid lengthy cycles, reduce cost effect

Inactive Publication Date: 2012-09-19
CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST
View PDF2 Cites 23 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the process of chip design, verification is a very important link. The full-scan verification of JTAG interface is the most commonly used method in verification. At present, hardware emulators, FPGA and other software and hardware collaborative products have appeared on the market. Although they are easy to develop and implement It has the characteristics of high speed and automatic compilation, but its cost is expensive, often hundreds of thousands or even millions, and there are defects such as long hardware debugging cycle and limited capacity. For the verification of large-scale design, it is impossible to realize the full chip (Full chip) Sufficiency and completeness of verification under the schema

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Software-hardware co-verification platform
  • Software-hardware co-verification platform
  • Software-hardware co-verification platform

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0012] Such as figure 1 Described, a kind of software-hardware co-verification platform, comprises upper computer, virtual online emulator ICE and tested design DUV and communication part, the communication between virtual online emulator ICE and upper computer is through the serial port between the server, and The test and design DUVs are connected by the programming language interface PLI, in which the upper computer is implemented on a server installed with a Linux operating system, and the virtual online emulator ICE, PLI interface, and the tested design DUV are implemented on another server installed with a Linux operating system. implemented on the server.

[0013] The upper computer mainly completes the work of generating verification data and comparing verification results; the virtual ICE is a C code program that completely imitates the functions realized by the online emulator, and is the core part of the entire test platform. The serial port and the programming lan...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a software-hardware co-verification platform, which comprises an upper computer, a virtual in-circuit emulator (ICE), a design under verification (DUV) and a communication part, wherein the virtual ICE communicates with the upper computer through a serial port between servers and is connected with the DUV through programming language interfaces (PLIs); the upper computer is realized on a server equipped with a Linux operating system; and the virtual ICE, the PLI and the DUV are realized on another server equipped with a Linux operating system. The verification environment of the verification platform can be realized only by using the servers with relatively large storage space, so that the problem of limited capacity of a software-hardware co-verification product is solved, and system-level verification of a chip at a design front end can be realized; the prices of the servers are low, so that the cost of integrated product development is reduced; and besides, as the software-hardware co-verification platform is completely realized by using software, a lengthy period of hardware debugging is avoided, the development process of the product is accelerated, and precious time is strived for early listing of the product.

Description

technical field [0001] The invention relates to a software-hardware cooperative verification platform, which is applied to the functional verification of large-scale hardware design at the front-end transfer level (Register Transfer Level, RTL). Background technique [0002] In the process of chip design, verification is a very important link. The full-scan verification of JTAG interface is the most commonly used method in verification. At present, hardware emulators, FPGA and other software and hardware collaborative products have appeared on the market. Although they are easy to develop and implement It has the characteristics of high speed and automatic compilation, but its cost is expensive, often hundreds of thousands or even millions, and there are defects such as long hardware debugging cycle and limited capacity. For the verification of large-scale design, it is impossible to realize the full chip (Full chip) The adequacy and completeness of verification under the mo...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/26
Inventor 李岩陆俊峰黄光红周乐郭二辉洪一
Owner CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products