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Harmonic attenuation method and circuit

A harmonic suppression and circuit technology, applied in the field of communication, can solve problems such as harmonic interference of radio frequency signals, and achieve the effect of suppressing different orders of harmonics and suppressing harmonics

Inactive Publication Date: 2015-01-21
HUNAN CHAIRMAN IND INTELLIGENT SYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] In view of the above-mentioned defects, the embodiment of the present invention provides a harmonic suppression method and circuit to solve the problem that the radio frequency signal is subjected to harmonic interference during the down-conversion process, and can flexibly suppress different orders of harmonics according to needs

Method used

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Experimental program
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Effect test

Embodiment 1

[0033] see figure 1 , figure 1 It is a basic flowchart of a harmonic suppression method provided by an embodiment of the present invention. The following will describe the embodiment of the present invention in detail from the perspective of the harmonic suppression circuit, as figure 1 As shown, the method includes the steps of:

[0034] 110. Input the radio frequency signal into the first working link and at least one second working link of the harmonic suppression circuit respectively;

[0035] The radio frequency signal will be interfered by harmonics during down-conversion, and the harmonic suppression circuit is selected to suppress the harmonics. The harmonic suppression circuit includes an adder, a first working link and at least one second working link, the first working link is a basic working link, and the first working link includes a first phase shifter and The first down-converter, the second working link includes a second phase shifter and a second down-conv...

Embodiment 2

[0046] Such as figure 2 As shown, the embodiment of the present invention also provides a harmonic suppression circuit, the circuit includes an adder 210, a first working link 220 and at least one second working link 230;

[0047] The first working link 220 includes a first phase shifter 221 and a first down-converter 222, the input end of the first phase shifter 221 is connected to the input source of the radio frequency signal, and the first phase shifter The output terminal of 221 is connected with the first input terminal of the first down-converter 222, the second input terminal of the first down-converter 222 is connected with the input source of the local oscillator signal, and the first down-converter The output end of device 222 is connected with the first input end of described adder 210;

[0048] The second working link 230 includes a second phase shifter 231, a second down converter 232 and a switch 233, the input end of the second phase shifter 231 is connected ...

Embodiment 3

[0058] Such as image 3 As shown, the following will start from the actual application scenario and take the total working link of the harmonic suppression circuit as n=4 as an example to illustrate that the harmonic with the maximum order of the seventh order can be suppressed, wherein the harmonic suppression circuit includes an adder , one first working link, and three second working links, the working principle is as follows:

[0059] The first working link includes a phase shifter and a down-converter, the second working link includes a phase shifter, a down-converter and a switch, the second working link is connected to the adder through the switch, and at the same time, through the control The switches in the second working link are opened or closed to suppress different orders of harmonics, including:

[0060] A1. When there is no need to suppress harmonics, the switches SW1, SW2, and SW3 are all disconnected, and only the first working link works;

[0061] A2. When ...

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Abstract

The embodiment of the invention discloses a harmonic attenuation method and a circuit. The method and the circuit are used for solving the problem of interference of different-order harmonics during a down-conversion process. The method provided by the embodiment of the invention comprises the steps: respectively inputting a same radio-frequency signal to a first active link and at least one path of second active link of a harmonic attenuation circuit; performing adjustment and phase shift on the radio-frequency signal inputted to the first active link by a first phase shifter, and then performing the down-conversion on the radio-frequency signal and a local oscillating signal inputted to a first down-converter; performing adjustment and phase shift on the radio-frequency signal inputted to the second active link by a second phase shifter, and then performing the down-conversion on the radio-frequency signal and the local oscillating signal inputted to a second down-converter; and lastly, adding the radio-frequency signals of all active links by an adder of the harmonic attenuation circuit, thereby efficiently attenuating the different-order harmonics.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a harmonic suppression method and circuit. Background technique [0002] In the down-conversion of frequency conversion technology, the down-converter mixes the received RF signal with the signal generated by the local oscillator, and uses the local oscillator signal to periodically control the conduction and disconnection of its internal circuit, so that the input RF signal passes through the down-converter After that, a discontinuous RF input signal is obtained at the output. If the RF input signal is U RF (t)=V RF cos(W RF t), where V RF Indicates the RF signal amplitude, W RF Indicates the RF signal frequency. With the positive and negative switching of the switching signal of the down-converter, the input signal is turned on and off at the output terminal, and the output signal is equivalent to the product of the RF input signal and the square wave switching sig...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03D7/16
Inventor 郭彩丽申朝阳曾志明冯淑兰
Owner HUNAN CHAIRMAN IND INTELLIGENT SYST CO LTD
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