Output buffer circuit
A technology for output buffering and circuits, applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, instruments, etc., which can solve problems such as device damage and overvoltage
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[0027] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0028] Such as image 3 As shown, the present invention is an output buffer circuit, which includes a rail-to-rail input module 1 , an AB output module 2 , a first voltage clamping module 3 and a second voltage clamping module 4 .
[0029] The rail-to-rail input module 1 is connected between the external power supply VDDA and the ground GNDA, and it includes a first MOS transistor M1, a second MOS transistor M2, a fifth MOS transistor M5 and a sixth MOS transistor M6, wherein,
[0030] The substrate of the fifth MOS transistor M5 is connected to the source, the substrate of the sixth MOS transistor M6 is connected to the source, and the sources of the fifth and sixth MOS transistors M5 and M6 are connected, and their gates respectively receive a positive voltage. Input voltage INP and a negative input voltage INN, the substrates and sources o...
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