Reset circuit of anti-fuse type FPGA (Field Programmable Gate Array) system

Abstract

The invention belongs to the technical field of a reset circuit, particularly relates to the reset circuit of an anti-fuse type FPGA (Field Programmable Gate Array) system, and aims at providing a circuit which can be reliably reset for the anti-fuse type FPGA system. The reset circuit of the anti-fuse type FPGA system comprises an external reset threshold circuit, a power-on reset signal generating circuit and an asynchronous reset signal generating circuit, wherein the external reset threshold circuit is connected with the asynchronous reset signal generating circuit for supplying an external reset signal for the asynchronous reset signal generating circuit, the power-on reset signal generating circuit is connected with the asynchronous reset signal generating circuit for supplying a power-on reset signal for the asynchronous reset signal generating circuit, and the asynchronous reset signal generating circuit receives the external reset signal and the power-on reset signal so as to generate an asynchronous reset signal. According to the reset circuit for the anti-fuse type FPGA system, disclosed by the invention, the asynchronous reset signal generating circuit is adopted, two stages of BUFFERs, a matching logic or a gate is simultaneously arranged, the competition adventure of an asynchronous reset signal edge and a clock edge is eliminated, and the asynchronous reset of the anti-fuse type FPGA system is realized.

Description

technical field [0001] The invention belongs to the technical field of reset circuits, and in particular relates to an antifuse type FPGA system reset circuit. Background technique [0002] The design method of the reset circuit in the existing FPGA system is to synchronize the asynchronous reset signal in the FPGA to generate a synchronous reset signal. When the effective edge of the clock signal introduced in the FPGA system changes, it resets the reset signal. . It should be noted that when the power is turned on, the stable output of the clock source and the power-on and configuration of the FPGA are the prerequisites for the synchronous reset to be effective. Due to the characteristics of the device itself, the general-purpose FPGA (such as the FPGA produced by xilinx company), the internal GSR signal automatically resets or sets all the registers and latches according to the design requirements at the end of the configuration. But for the anti-fuse FPGA, the internal...

AI Technical Summary

Problems solved by technology

However, for anti-fuse FPGAs, the internal registers are not automatically configured at power-on

This kind of reset circuit is not suitable for anti-fuse FPGA, and it is only a synchronous reset, which cannot realize the asynchronous reset required by anti-fuse FPGA.

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