Array substrate, manufacture method thereof and liquid crystal panel
A technology of an array substrate and a manufacturing method, which is applied to the field of array substrates with a narrow frame design, can solve the problems of reducing the utilization rate of a liquid crystal display panel, increasing the size of the frame area 320, etc., and achieves the improvement of display quality, competitiveness and utilization. Effect
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no. 1 example
[0041] refer to Figure 5 , is a schematic top view structure diagram of the array substrate according to the first embodiment of the present invention.
[0042] The array substrate is divided into a display area I and a frame area II surrounding the display area. To simplify the illustration, Figure 52 only shows a schematic top view of the border area of the display area I and the frame area II. The array substrate includes: a glass substrate, multiple scanning lines on the glass substrate: scanning line 101, scanning line 103, scanning line 105, etc., multiple data lines: data line 102, data line 104, data line 106, etc. The scan lines and the data lines are orthogonal and insulated from each other, the data lines are located above the scan lines, and the two divide the display area into a plurality of pixel areas arranged in an array, and each pixel area includes a thin film transistor 110 and pixel electrode 130 .
[0043] Figure 5 The array structure in has 2 row...
no. 2 example
[0054] In the above embodiment, when the scanning connection line and the scanning line extend to the frame area II, they still overlap in the light transmission direction, and a via hole can be directly formed in the frame area II to connect them. Usually, due to the limited width of the scanning connection line and the scanning line, there may be problems of difficult alignment and poor contact when making the via hole, or the problem of disconnection of the scanning line or the scanning connection line. Offset or even failure or disconnection of the line will cause the column of pixel areas controlled by the scan line to fail to work normally. Therefore, the present invention also provides a second embodiment to solve the above problems.
[0055] refer to Figure 6 As shown in FIG. 2 , it is a schematic top view structure diagram of the array substrate according to the second embodiment of the present invention. Will Figure 6 and Figure 5 It can be seen from the compa...
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