Packaging structure for ball grid array and manufacturing method for same

Abstract

The invention relates to a packaging structure for a multi-chip ball grid array and a manufacturing method for the same, wherein the packaging structure for a ball grid array comprises a substrate; at least two chips fixed on the upper surface of the substrate and the lower surface of the substrate respectively, wherein a signal end is formed on each chip; pad parts disposed on the upper surface and the lower surface of the substrate and provided with through holes penetrating through the substrate in a thickness direction, wherein the pad parts form electric connections with the signal ends via leads; conducting parts which are conducting pins inserted and fixed in the through holes; and plastic packaging parts for protecting the substrate, the conducting parts and the chips. According to the packaging structure for a multi-chip ball grid array and the manufacturing method for the same disclosed by the invention, the generation for a cantilever in a multi-chip packaging can be reduced, the manufacturing technique can be simplified, and a warping phenomenon in structure can be prevented.

Description

technical field [0001] The present invention relates to a ball grid array packaging structure and a manufacturing method thereof, in particular to a ball grid array packaging structure and a packaging structure of a multilayer chip by arranging chips on the upper surface and the lower surface of a substrate and leading out an internal circuit through a conductive part. Manufacturing method. Background technique [0002] Ball grid array (BGA) packaging technology is a surface mount package that replaces traditional lead frames by making ball bumps in an array on the back of the substrate, making semiconductor devices more integrated. , better performance. BGA packaging technology will significantly increase the number of I / O pins of the device, reduce the pad pitch, and then reduce the size of the package and save the footprint of the package, so that the high density of PC chipsets, microprocessors, etc., Miniaturization of high-performance, multi-pin packaged devices is p...

AI Technical Summary

Problems solved by technology

[0007] 1) When the sizes of multiple chips are inconsistent and the size of the chip placed on the upper side is larger, a cantilever structure will be generated, which makes the wire bonding process more difficult, especially when the size of the cantilever protrudes is large , so this process is easily limited by the size of the chip;

[0008] 2) In the existing process, the first chip is first bonded to the substrate, then the first chip is subjected to a wire bonding process, and then the second chip is arranged on the upper side of the first chip, and then the The second chip performs the wire bonding process, so the process program needs to be carried out back and forth, the program is complicated, and the time consumed is relatively long;

[0009] 3) Since the chip is only arranged on one side of the substrate, the package structure is prone to structural warpage, especially when the overall size is thin

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