Mixed-value based sexenary adiabatic asynchronous adding/subtracting counter units and counter

An addition, subtraction, and counter technology, which is applied in the field of six-value adiabatic asynchronous addition and subtraction counter units and counters, can solve the problems of MOS tube threshold detection difficulties, high power supply voltage, etc.

Inactive Publication Date: 2012-02-22
NINGBO UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the past, most of the research on multi-valued logic circuits focused on three-valued or four-valued logic circuits, while there were relatively few studies on six-valued logic circuits. However, the direct design of six-valued logic circuits not only requires a higher power supply voltage, but also requires MOS It is quite difficult to detect the threshold value of the tube, so it is of practical significance to study the six-valued logic circuit with low power consumption and high working reliability

Method used

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  • Mixed-value based sexenary adiabatic asynchronous adding/subtracting counter units and counter
  • Mixed-value based sexenary adiabatic asynchronous adding/subtracting counter units and counter
  • Mixed-value based sexenary adiabatic asynchronous adding/subtracting counter units and counter

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Embodiment 1

[0021] Embodiment 1: For a one-bit six-value signal, if a binary signal is used for encoding, three binary signals are required, and the encoding efficiency is 6 / 2 3 =75%, resulting in 2 redundant items, resulting in a waste of coding, which not only increases the IC chip area and production cost, but also reduces the data processing speed and affects the reliability of circuit work. If 2-3 mixed-value coding is introduced, only one bit of binary signal and one bit of three-valued signal are needed, as shown in Table 1, where a 2 Represents a binary signal (0, 2), a 3 Represents a three-valued signal (0, 1, 2), a binary signal a 2 The highest logical value of 2 and the three-valued signal a 3 The levels corresponding to the highest logic value of 2 are equal. It can be found from Table 1 that the 2-3 mixed value coding does not have any redundant states, and the coding efficiency reaches 100%.

[0022] Table 12-3 Mixed value encoding

[0023]

[0024] According to the ...

Embodiment 2

[0030] Embodiment two: a kind of six-value adiabatic asynchronous addition and subtraction counter based on the mixed value (2-3 mixed value) six-value adiabatic asynchronous addition and subtraction counter unit based on the mixed value (2-3 mixed value) given in embodiment one constitutes, including N A six-value adiabatic asynchronous addition and subtraction counter unit based on a mixed value, an N-1 six-value adiabatic carry / borrow circuit 3 and a six-value adiabatic carry / borrow circuit 3 set at the i-th bit and the i+1-th bit based on DTCTGAL buffer 4 between the mixed-valued six-valued adiabatic asynchronous addition and subtraction counter unit, the i-th bit based on the mixed-valued six-valued adiabatic asynchronous asynchronous addition and subtraction counter unit’s first up count output and the i-th bit six-valued adiabatic The binary signal input terminal of the carry / borrow circuit 3 is connected to the second addition and counting output terminal of the i-th bi...

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Abstract

The invention discloses a mixed-value based sexenary adiabatic asynchronous adding / subtracting counter which comprises N mixed-value based sexenary adiabatic asynchronous adding / subtracting counter units, N-1 sexenary adiabatic carry / borrow circuits, and a DTCTGAL (double power clock ternary clocked transmission gate adiabatic logic) buffer, wherein the DTCTGAL buffer is arranged between the ith sexenary adiabatic carry / borrow circuit and the (i+1)th mixed-value based sexenary adiabatic asynchronous adding / subtracting counter unit, and each mixed-value based sexenary adiabatic asynchronous adding / subtracting counter unit is composed of a sexenary adiabatic right-shift door and a sexenary adiabatic D trigger. The counter disclosed by the invention has the advantages that according to a theory of three essential circuit elements, an adiabatic technique is introduced into a design on sexenary logic circuits, and the design on a mixed-value (2-3 mixed values) based sexenary adiabatic asynchronous adding / subtracting counter is implemented by using a mixed-value coding technique, so that an effect of energy consumption saving is significantly achieved, and the counter has a characteristic of high information density; and compared with a conventional sexenary adiabatic asynchronous adding / subtracting counter, by using the counter disclosed by the invention, about 94% of energy consumption can be saved.

Description

technical field [0001] The invention relates to an addition and subtraction counter, in particular to a mixed value-based six-value adiabatic asynchronous addition and subtraction counter unit and a counter. Background technique [0002] Internationally, much attention has been paid to the development of digital logic systems with high information density and the enhancement of their information processing capabilities. One of the important research directions is multi-valued logic. Multi-valued logic circuits can not only increase the ability of a single line to carry information and increase the information density of digital circuits, but also reduce the chip area and pin count of integrated circuits and reduce production costs. In the past, most of the research on multi-valued logic circuits focused on three-valued or four-valued logic circuits, while there were relatively few studies on six-valued logic circuits. However, the direct design of six-valued logic circuits n...

Claims

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Application Information

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IPC IPC(8): G06F7/50
Inventor 汪鹏君梅凤娜
Owner NINGBO UNIV
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