Integrated circuit and integrated circuit method

Abstract

An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level.

Description

technical field [0001] The present invention relates to integrated circuits. In particular, it relates to circuits of static random access memory (SRAM) on a semiconductor substrate. Background technique [0002] Semiconductor memory devices are continually being designed to be smaller, faster, and require less power to facilitate portable devices using battery power. SRAM is a volatile memory widely used in laptops and personal digital assistants (PDAs), in which each memory cell includes a transistor base bistable latch (transistor -based bistable latch), which is either in the "conducting" state or in the "non-conducting" state. SRAM devices may include a matrix of thousands of individual memory cells fabricated on an integrated circuit chip. [0003] When data is not read or written in the SRAM array in the standard operating state, the leakage current causes the traditional SRAM array to have high power consumption. In order to reduce leakage current and power consu...

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Problems solved by technology

Self-biased diodes suffer from reductions in storage voltage due to critical voltage changes due to process, voltage, and temperature variations

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