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Instruction processing method of network processor and network processor

A network processor and instruction technology, applied in the direction of electrical digital data processing, address formation of the next instruction, instruments, etc., can solve the problems of reducing the performance of the main line process and prolonging the instruction execution cycle, so as to save the execution cycle, reduce the impact, easy-to-achieve effects

Active Publication Date: 2011-12-21
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In the process of realizing the present invention, the inventor found that the above-mentioned prior art has at least the following disadvantages: when the network device has additional features, the judgment jump instruction added in the main line flow will prolong the execution cycle of the instruction, thereby reducing the main line flow. performance

Method used

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  • Instruction processing method of network processor and network processor
  • Instruction processing method of network processor and network processor
  • Instruction processing method of network processor and network processor

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0026] see figure 1 , this embodiment provides a network processor instruction processing method, including:

[0027] 101: When the network processor executes the pre-added combination function call instruction, add the address of the next instruction of the combination function call instruction to the stack top of the first stack; wherein, the first stack is preset for combination stack of function calls;

[0028] 102: Determine whether the enable flag of each additional feature of the network processor is enabled according to the combined function call instruction, and if the enable flag of the additional feature is enabled, add the function entry address corresponding to the additional feature to the top of the first stack;

[0029] 103: After the judgment of the enable flags of all additional features is completed, the function entry address added to the first stack is popped from the top of the stack, and the function corresponding to the popped function entry address i...

Embodiment 2

[0032] see figure 2 , this embodiment provides a network processor instruction processing method, including:

[0033] 201: Store enable flags of all additional features of the network processor in the first register in advance.

[0034] In this embodiment, there may be one or more additional features of the network processor, and generally there are more than one. When there are multiple additional features, they may be all enabled, partially enabled, or not enabled at all, which is not specifically limited in this embodiment of the present invention.

[0035]The enable flag of the additional feature is usually a 1-bit flag with two value ranges, representing enable and disable respectively. For example, when the value is 1, it means enabled, and when the value is 0, it means disabled. The embodiment of the present invention does not limit the specific value of the enable flag.

[0036] The first register in this embodiment may be a general-purpose register with a length ...

Embodiment 3

[0064] see Figure 7 , this embodiment provides a network processor, including:

[0065]The first processing module 701 is used to add the address of the next instruction of the combined function call instruction to the stack top of the first stack when the network processor executes the pre-added combined function call instruction; according to the combined function call instruction, judge Whether the enable flag of each additional feature of the network processor is enabled, if the enable flag corresponding to the additional feature is enabled, the function entry address corresponding to the additional feature is added to the stack top of the first stack; wherein, The first stack is a preset stack used for combining function calls;

[0066] The second processing module 702 is used to pop the function entry address added to the first stack from the top of the stack after the judgment of the enable flags of all additional features is completed, and execute the function corres...

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Abstract

The invention provides an instruction processing method of a network processor and a network processer. The method comprises the steps of when the network processor executes a pre-added composite function, adding the address of a next instruction to the stack top of a first stack, judging whether the enabling signs of each additional characteristic is enabled or not according to a calling instruction of the composite function, if the enabling signs of each additional characteristic is enabled, adding the function entrance address of the corresponding additional characteristic to the stack top of the first stack, when all the enabling signs are judged, poping the function entrance addresses in the first stack from the stack top, and executing the functions to which the poped function entrance addresses correspond, until the address of the next instruction is poped. The network processor comprises a first processing module and a second processing module. In the invention, a judging skip instruction is just needed to be added in a main flow, the functions of all the enabled additional characteristics can be called, saving the instruction execution period substantially, and reducing the effects of main characteristics on the additional characteristics.

Description

technical field [0001] The invention relates to the field of network processors, in particular to an instruction processing method of the network processor and the network processor. Background technique [0002] A network processor is a type of processor specially designed for forwarding data packets, and is widely used as a forwarding engine in network devices such as routers and switches. Since the total number of code instructions of network processors is much smaller than that of general-purpose processors, and network processors have high requirements for forwarding performance, especially throughput, most network processors have all code instructions located in the processor during operation. in the internal high-speed memory. On a network device with a network processor as the forwarding engine, the forwarding performance of a specific service is usually inversely proportional to the sum of the instruction cycles executed by the service in the network processor, and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/32
CPCG06F9/322G06F9/32G06F9/4426G06F9/44G06F9/4486G06F9/323
Inventor 尹高嵩韩冰
Owner HUAWEI TECH CO LTD
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