Quad flat no-lead package and manufacturing method thereof

Abstract

The invention provides a method for manufacturing a quad flat no-lead package, comprising the following steps: providing a motherboard; forming a mold layer on the upper surface of the motherboard; forming a through hole penetrating to the upper surface of the motherboard on the surface of the mold layer, The opening area of ​​the through hole close to the upper surface of the motherboard is smaller than the opening area of ​​the other side; the chip tray and the chip electrode are formed in the through hole; the chip is fixed on the surface of the chip tray; between the chip and the chip electrode forming electrical leads between them; forming a plastic package on the upper surface of the motherboard; removing the motherboard to expose the chip tray and chip electrodes embedded in the plastic package.

Description

technical field [0001] The invention relates to the field of packaging and testing of semiconductor devices, in particular to a quadrilateral flat leadless package and a manufacturing method thereof. Background technique [0002] In everyday life, consumers demand more and more reliability, size, and price from products such as personal phones, personal digital assistants, and music players. For example, consumers want their personal phones to be ultra-thin and reliable. This requires packaged devices to be smaller and have fewer defects. In addition, these small form factor requirements may also require electronic components that dissipate heat from the packaging structure. [0003] Quad flat no-lead package is a common packaging method in the prior art. The method is a standard packaging method using one lead frame and one die. attached figure 1 Shown is a schematic cross-sectional view of a typical QFN package structure in the prior art, including a chip 10 , a chip ...

AI Technical Summary

Problems solved by technology

[0004] attached figure 1 The disadvantage of the prior art shown is that the chip electrode is easy to come out of the plastic package, especially when the chip is working due to temperature changes and the deformation between the chip electrode and the plastic package due to the difference in thermal expansion coefficient occurs. , this phenomenon is particularly obvious, and due to the thermal expansion coefficient mismatch between the chip tray and the chip electrode and the plastic package, it will cause serious thermal stress residual problems

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