Wafer-level packaging structure and method of forming the same

Abstract

The invention provides a wafer level package structure and a formation method thereof. The method comprises the following steps: providing a substrate; forming a cavity in the substrate; forming a redistribution line in the substrate and on part surface of the cavity; providing a chip to be packaged, wherein the chip has a device surface and a basal surface opposite to the device surface; formingan Under Bump Metal on a soldering pad layer surface of the device surface and forming a bump on a surface of the Under Bump Metal; connecting the chip to be packaged with the substrate such that thechip to be packaged faces the cavity and the bump is electrically connected with the redistribution line. The wafer level package structure in the invention has the advantages of a simple structure, high packaging quality, and high compatibility in subsequent combination with PCB plate process. The wafer level package structure formation method in the invention has the advantages of simple process sequence and low cost.

Description

technical field [0001] The invention relates to the field of chip packaging, in particular to a wafer-level packaging structure and a forming method thereof. Background technique [0002] As the size of the chip becomes smaller and the function becomes stronger, the number of pads increases and the spacing between the pads continues to narrow. Correspondingly, higher requirements are put forward for the chip package. [0003] The traditional chip packaging method usually uses wire bonding (Wire Bonding) for packaging, but with the rapid development of chips, wafer level packaging (Wafer Level Package, WLP) gradually replaces wire bonding. More information on wafer-level packaging can be found in the patent documents, please refer to figure 1 , the existing wafer-level packaging structure, comprising: a substrate 2, the substrate 2 has a first pad 3 located on the first surface of the substrate 2, a second pad 3 located on the second surface of the substrate 2 pad 18, and t...

AI Technical Summary

Problems solved by technology

[0004] However, the wafer-level packaging of the prior art needs to embed the chip 6 to be packaged into the package substrate 2 (receptacle 4), and the chip 6 to be packaged will be strictly matched to the package structure, so that the size of the package structure is subject to The packaged chip 6 has large restrictions, and the existing wafer-level packaging process is complicated, which requires high wafer-level packaging technology

Images