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Method for hierarchically describing configuration information of dynamic reconfigurable processor

A technology for configuring information and processors, which is applied in the direction of electrical digital data processing, instruments, computers, etc., and can solve the problems of excessive storage and transmission of configuration information

Active Publication Date: 2013-05-22
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] At present, there are often problems of excessive storage and transmission of configuration information in dynamic reconfigurable processors. Therefore, the present invention innovatively proposes a method for hierarchically describing configuration information of dynamic reconfigurable processors to meet the needs of practical applications. needs

Method used

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  • Method for hierarchically describing configuration information of dynamic reconfigurable processor
  • Method for hierarchically describing configuration information of dynamic reconfigurable processor
  • Method for hierarchically describing configuration information of dynamic reconfigurable processor

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Embodiment

[0071] refer to figure 2 , shows a flowchart of a method for hierarchically describing configuration information of a dynamically reconfigurable processor according to the present invention, the method specifically includes:

[0072] Step S201, the selection information of the arithmetic logic function of each processing unit, the input selection information of each processing unit, and the timing control information of the processing unit array are stored in the on-chip memory as configuration information level 3;

[0073] Step S202, the configuration information of the array, the configuration information of the internal and external data conversion device, the configuration information of the internal data reading device, and the configuration information of the internal data writing device are stored in the on-chip memory as configuration information level 2;

[0074] Step S203, the configuration information of the inter-subunit data interaction device and the subunit con...

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Abstract

The invention provides a method for hierarchically describing configuration information of a dynamic reconfigurable processor. In the method, the configuration information of the dynamic reconfigurable processor is hierarchically stored in an in-chip memory, so that storage space of the configuration information in the in-chip memory is effectively saved, and quantity of the configuration information transmitted to the dynamic reconfigurable processor by a master processor is reduced.

Description

technical field [0001] The invention relates to the technical field of embedded systems, in particular to a method for hierarchically describing configuration information of a dynamically reconfigurable processor. Background technique [0002] Dynamic reconfigurable processor is a new processor architecture, which has significant advantages over previous single-core processors, dedicated chips, and field programmable logic arrays, and is a direction for the development of future circuit structures. [0003] First of all, a dynamically reconfigurable processor often contains multiple arithmetic logic units, and the number is huge, which is called a many-core array. The array is equipped with a highly flexible routing unit to realize the diversified interconnection between the arithmetic and logic units. Therefore, the many-core array connected by the routing unit can realize high-speed processing of data streams, and has a huge advantage in performance compared with traditio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/177
Inventor 王延升刘雷波朱敏戚斌杨军曹鹏时龙兴尹首一魏少军
Owner TSINGHUA UNIV
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