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A sample-and-hold amplifier

A sample-and-hold, amplifier technology, used in amplifiers, amplifiers using switched capacitors, amplifiers with semiconductor devices/discharge tubes, etc., can solve problems such as unrealistic time interleaving of front-end sample-and-hold amplifiers

Inactive Publication Date: 2011-09-21
NXP BV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Time interleaving is a common technique to increase the sampling rate, although, for high resolution ADCs, time interleaving of front-end sample-and-hold amplifiers (SHAs) may not be practical due to strict time alignment requirements

Method used

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Examples

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Embodiment Construction

[0037] One or more embodiments described herein relate to a sample-and-hold amplifier that operates according to a sample phase of operation and a hold phase of operation. Track-and-hold amplifiers include amplifiers such as operational transconductance amplifiers (OTAs), which in conventional approaches can be used to buffer the input signal during the hold phase of operation and can also be used to precharge the output of the track-and-hold amplifier during the sample phase of operation. Such an embodiment may eliminate the need for an additional buffer to precharge the output during the sample phase of operation by utilizing OTA that would otherwise not be used during the sample phase of operation. This will result in a more efficient track-and-hold amplifier, since fewer components are required and / or the power consumption of the track-and-hold amplifier can be reduced.

[0038] In some embodiments, a Miller topology amplifier can be used as part of a sample-and-hold ampli...

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PUM

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Abstract

A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample,and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.

Description

technical field [0001] The present invention relates to the field of sample-and-hold amplifiers, and in particular but not exclusively, to a sample-and-hold amplifier having a hold phase of operation and a sample phase of operation, which sample-and-hold amplifier may be used with a time-interleaved analog-to-digital converter. Background technique [0002] For high-resolution analog-to-digital converters (ADCs), higher sampling rates are the trend. Time interleaving is a common technique to increase the sampling rate, although, for high-resolution ADCs, time interleaving of the front-end sample-and-hold amplifier (SHA) may not be practical due to strict time alignment requirements. "A CMOS 33-mW100-MHz 80-dB SFDR Sample-and-Hold Amplifier" by C-C Hsu and Wu J-T (VLSI CircuitsSymp.Dig., pp. 263-264, 2003) discloses a high-rate High-resolution sample-and-hold amplifier (SHA). [0003] "A CMOS 15-bit125-MS / s Time-Interleaved ADC With Digital Background Calibration" by Z-M Le...

Claims

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Application Information

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IPC IPC(8): H03M1/54
CPCH03F2200/129H03F2200/156H03F2203/45512H03F2203/45551H03F2203/45616H03F3/45475H03F3/005H03F2200/159H03F2203/45536H03F2203/45514H03F2200/135H03F2203/45534
Inventor 贝里·A·J·巴特汉斯·文德卫尔
Owner NXP BV
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