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Semiconductor device and method for manufacturing same

A semiconductor and n-type technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as increased channel resistance, decreased threshold voltage, and reduced withstand voltage, achieving low channel resistance and low channel resistance. The effect of channel resistance reduction

Inactive Publication Date: 2011-09-14
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] However, the inventors of the present application found after research that if Figure 10 As shown, if the boundary portion 27b with a high impurity concentration is provided on the surface of the drift layer 3, the following four problems will arise: (1) increase of drain leakage in the off state; (2) breakdown voltage in the off state reduction; (3) destruction of the gate insulating film or generation of leakage current in the gate insulating film caused by a high drain electric field in the off state; and (4) reduction of the threshold voltage
As a result, the channel resistance increases

Method used

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  • Semiconductor device and method for manufacturing same
  • Semiconductor device and method for manufacturing same
  • Semiconductor device and method for manufacturing same

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no. 1 Embodiment approach

[0056] Hereinafter, a first embodiment of the semiconductor device of the present invention will be described. In this embodiment mode, a double injection type MOSFET will be described as an example. figure 1 (a) shows a cross-sectional structure of a part of the double injection type MOSFET 101, figure 1 (b) shows the planar structure of the drift layer 3 of the MOSFET101. figure 1 (a) means figure 1 In the cross-sectional structure of line 1A-1A in (b), MOSFET 101 includes a plurality of lattice units U. like figure 1 As shown in (b), on the drift layer 3 , each lattice unit U has, for example, a square shape, and the lattice units U are arranged in a zigzag shape. More specifically, the lattice units U are arranged two-dimensionally, and the arrangement of the lattice units U is shifted by 1 / 2 cycle in one direction. However, as will be described below, in MOSFET 101, the effect of the present invention can be obtained if lattice units U are arranged adjacent to e...

no. 2 Embodiment approach

[0110] Hereinafter, a second embodiment of the semiconductor device of the present invention will be described. Figure 7 (a) shows a cross-sectional structure of a part of the double injection type MOSFET 102, Figure 7 (b) shows a plan view of the drift layer 3 of the MOSFET 102 . Figure 7 (a) means Figure 7 The cross-sectional structure of line 6A-6A in (b). exist Figure 7 In (b), the structure of the cross-section shown by the line 1A-1A is the same as that of the first embodiment. Similar to the first embodiment, MOSFET 102 includes a plurality of lattice units U, and on drift layer 3, each lattice unit U has a square shape, and the square shape is arranged in a zigzag shape.

[0111] like Figure 7 As shown in (a) and (b), the difference between the MOSFET 102 and the first embodiment is that in the drift layer 3, it is adjacent to the fourth n-type impurity region 7d, and in the apex of the lattice unit U, There is also a fifth n-type impurity region 31 in plac...

experiment example

[0116] Hereinafter, in MOSFET 101 according to the first embodiment, experimental results regarding the effect on channel resistance when the impurity concentrations of the third n-type impurity region and the well are changed will be described.

[0117] like Figure 7 As shown, the size of the lattice unit is set as Xcell, and the distance between the first n-type impurity regions 5 and the distance between the second n-type impurity regions 7a of two adjacent lattice units in the arrangement direction of the lattice units is The distances are set to a+2Lg and a respectively. The width of the second n-type impurity region 7a in the arrangement direction of the grid cells is represented by Lg which is the channel length. Table 1 shows the values ​​used in the calculation.

[0118] (Table 1)

[0119]

[0120]

[0121] Figure 8 shows the channel resistance Rch when the carrier concentration Na of the first n-type impurity region 5 and the impurity concentration Next of ...

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Abstract

Each unit cell comprises a drift layer (3) composed of an n-type wide band gap semiconductor and formed on a substrate (2) which is composed of an n-type wide band gap semiconductor, a p-type well (4a) formed within the drift layer (3), a first n-type impurity region (5) formed within the well (4a), a surface channel layer (7b) formed at least on the surface of the well so as to connect the first n-type impurity region (5) and the drift layer (3), a second n-type impurity region (7a) which is formed below the surface channel layer within the well in the surface region ranging from the first n-type impurity region (5) to the drift layer (3) and has an impurity concentration almost equal to or higher than the impurity concentration of the well (4a), and a third n-type impurity region formed in the surface region of the drift layer (3) so as to be adjacent to the second n-type impurity region (7a).

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a silicon carbide semiconductor device and a manufacturing method thereof. Background technique [0002] Wide bandgap semiconductors are attracting attention as semiconductor materials for semiconductor devices (power elements) that have high withstand voltage and can flow large currents. Since silicon carbide (silicon carbide: SiC) has a particularly high dielectric breakdown electric field even among wide bandgap semiconductors, it is expected to be the most suitable semiconductor for next-generation low-loss power devices. Better quality silicon dioxide (SiO2) can be formed on SiC due to thermal oxidation 2 ) film, and therefore, the development of an insulated gate type SiC-power-MOSFET using such a silicon dioxide film as a gate insulating film is progressing. [0003] In the case of fabricating SiC-power-MOSFETs, ion implantation is used to control the conductivity of the semicon...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/12H01L21/265H01L21/336H01L29/78
CPCH01L29/66068H01L21/047H01L29/0696H01L29/4238H01L29/1608H01L29/7828
Inventor 山下贤哉
Owner PANASONIC CORP
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