Internuclear communication method of multinuclear processor and circuit structure thereof

Abstract

The invention belongs to the technical field of a high-performance processor and particularly relates to an internuclear communication method of a multinuclear processor and a circuit structure thereof. In the communication method provided by the invention, functional expansion is performed on a register circuit module in the existing multinuclear processor architecture, and an internuclear communication address mapping unit is added in the module, thereby realizing the access to an internuclear communication address by accessing a register address and realizing the rapid access to the internuclear communication address and the rapid interaction of the internuclear data. The circuit structure provided by the invention comprises an expansion register circuit module, an FIFO (First In First Out) queue circuit module, a data route array circuit module, an internuclear communication control circuit module and a processor functional circuit module, and the circuit structure is divided into three data link levels. The internuclear communication method and the circuit structure thereof prompt the communication efficiency and operation efficiency of the existing multinuclear processor and have obvious academic value and practical value.

Description

technical field [0001] The invention belongs to the technical field of high-performance processors, and specifically relates to an inter-core communication method and circuit structure suitable for multi-core processors. Background technique [0002] Since 2000, there has been a boom in multi-core processors. Under the circumstances that the traditional single-core processor clock cannot be further improved, the difficulty of deep submicron design is increasing, and the progress of semiconductor technology is slowing down, multi-core processors have attracted great attention from designers. At present, almost all mainstream processors on the market are multi-core processor architectures. Compared with traditional single-core processors, multi-core processors have stronger parallel computing capabilities, better scalability and configurability, and have certain advantages in power consumption. In essence, a multi-core processor uses a certain network topology to connect a c...

AI Technical Summary

Problems solved by technology

However, in the on-chip network architecture, due to the complex network topology, the data communication efficiency between processor cores is not high, which has become a bottleneck that limits the performance improvement of multi-core processors.

At present, many institutions and individuals have proposed their own solutions for inter-core communication methods, but there is still no conclusion on the optimal solution.

Images