High-speed low-power consumption latch device capable of resisting SEU (single event upset)

Abstract

The invention is suitable for the field of semiconductor devices and provides a high-speed low-power consumption latch device capable of resisting SEU (single event upset). The latch comprises a first latch unit and a second latch unit, which are cross-coupled, wherein a clock signal of the first latch unit is opposite to the clock signal of the second latch unit; a data signal of the first latch unit is opposite to the data signal of the second latch unit; when a stored data value at a sensitive point of the first latch unit upsets, the stored data value at the sensitive point of the first latch unit is recovered by the second latch unit through feedback; and when the stored data value at the sensitive point of the second latch unit upsets, the stored data value at the sensitive point of the second latch unit is recovered by the first latch unit through feedback. In the invention, a redundancy storage node is introduced in the high-speed low-power consumption latch device capable of resisting SEU under a common process condition, and when a node upsets, the voltage of the node can be recovered from other nodes through feedback.

Description

technical field [0001] The invention belongs to the field of semiconductor devices, in particular to an anti-single-event flipping high-speed and low-power consumption latch. Background technique [0002] With the rapid development of aerospace technology, more and more semiconductor devices are used in electronic control systems in the aerospace field. In outer space, there are cosmic rays composed of various rays and single heavy ions. These cosmic rays can cause damage to the electronic control system composed of conventional semiconductor devices. The damage renders it ineffective or even crashes. As the basic instruction storage device of these electronic control systems, its anti-radiation ability is particularly important. Because once the data in the device is wrong, it will directly lead to the failure of the entire system. figure 1 It is an unreinforced latch circuit diagram, in which the size of PMOS transistor P35 and PMOS transistor P36 is smaller than that o...

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Problems solved by technology

Under the same conditions, the static current of Rockett's structure is large; the number of tubes in Liu's structure is more, the connection relationship is more complicated, and the area requirement is larger; the structure of Haddad has many sensitive points, which is easy to flip and not easy to restore

[0007] In short, in the current common anti-radiation scheme, process reinforcement can effectively reduce the charge collection on the single particle track, but the process cost is high, there are few process lines to choose from, and the integration is usually behind the commercial process; the resistance reinforcement scheme can be used Ordinary commercial process, but it needs to add a special mask layer to make polysilicon resistors, more importantly, resistance reinforcement will significantly reduce the writing speed of memory cells; some flips in the design reinforcement scheme are not easy to recover or flip recovery Long time, some area requirements are large, and some quiescent current is large

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