Asynchronous counter circuit and realizing method thereof

Abstract

The invention discloses an asynchronous counter circuit and a realizing method thereof. The asynchronous counter circuit comprises a trigger cascade circuit, a numerical value comparison circuit and a counter reset signal processing circuit, wherein the trigger cascade circuit realizes a basic counting function; when a count value reaches a design value, the numerical value comparison circuit generates a mark signal; after the mark signal passes through the counter reset signal processing circuit, a stable and effective reset signal can be generated for resetting a trigger in the trigger cascade circuit; therefore, a set counting function is realized. By using the circuit given by the invention, the phenomenon that the reset of the asynchronous counter circuit is unreliable is solved, andthe stability and the reliability of the circuit are improved.

Description

technical field [0001] The invention relates to an asynchronous counter circuit and method. It can be used in the design of integrated circuits that need to realize the counting function and have low power consumption requirements. Background technique [0002] A counter circuit is one of the most basic circuits often used in integrated circuit design. According to the different clock pulse input methods, it can be divided into synchronous counters and asynchronous counters. All flip-flops in the synchronous counter circuit work on the count clock, and the control logic is relatively complex, so the power consumption is relatively large. In the asynchronous counter circuit, usually only the first-stage flip-flop works on the counting clock, and the power consumption is relatively small. [0003] In a common asynchronous counter circuit structure, when the count value reaches the design value, the reset signal generated by the decoding circuit will reset the count flip-flo...

AI Technical Summary

Problems solved by technology

In the circuit of this structure, there are two problems: 1. The reset signal itself generated by the decoding circuit may have glitches due to the risk of competition in the combinational logic, resulting in a false reset signal, thus making the circuit unstable.

2. The time when the reset signal arrives at each counting flip-flop is different. Some flip-flops may have been reset, and some flip-flops have not been reset.

At the same time, the limitation of system cost also makes designers pay more and more attention to low power consumption design

Images