Partial SOI (silicon on insulator) traverse double-diffused device

Abstract

The invention relates to the SOI (silicon on insulator) technology. The invention solves the problem that the heating effect of the existing conventional SOI device is obvious, and provides a partial SOI traverse double-diffused device. The technical scheme of the invention is summarized as follows: one end of an oxide buried layer of the partial SOI traverse double-diffused device is arranged below a source electrode and is contacted with the edge of the device, the horizontal distance between the other end of the oxide buried layer and a drain type II impurity ohm contact area is not less than zero, a PN (phosphorus-nitrogen) junction is formed by the way that a type I impurity substrate is contacted with the silicon layer of the type II impurity top layer between the other end of the oxide buried layer and the edge of the device below the drain. The partial SOI traverse double-diffused device has the beneficial effects that the oxide buried layer is provided with an opening below the drain, the heat produced by an SOI device can be effectively transferred, and the partial SOI traverse double-diffused device is applicable to SOI devices.

Description

technical field [0001] The invention relates to SOI technology, in particular to an SOI lateral double-diffusion device. Background technique [0002] SOI (Silicon on Insulator) technology is known as "silicon integrated circuit technology in the 21st century". It is one of the mainstream technologies of the new generation of integrated circuits. The LOCOS process is used for the full dielectric isolation device. The thin-film SOI is isolated by the LOCOS process. There is no well preparation, and the formation of silicon islands can be realized by local oxidation, which greatly reduces the area of ​​the isolation region. However, the vertical withstand voltage of conventional SOI devices It is only determined by the drift region and the buried oxide layer, and its serious self-heating effect limits its development. Park et al. proposed a partial SOI device structure. Due to the existence of silicon windows, the drift region is connected to the substrate, and the depletion l...

AI Technical Summary

Problems solved by technology

[0002] SOI (Silicon on Insulator) technology is known as "silicon integrated circuit technology in the 21st century". It is one of the mainstream technologies of the new generation of integrated circuits. The LOCOS process is used for the full dielectric isolation device. The thin-film SOI is isolated by the LOCOS process. There is no well preparation, and the formation of silicon islands can be realized by local oxidation, which greatly reduces the area of ​​the isolation region. However, the vertical withstand voltage of conventional SOI devices It is only determined by the drift region and the buried oxide layer, and its serious self-heating effect limits its development. Park et al. proposed a partial SOI device structure. Due to the existence of silicon windows, the drift region is connected to the substrate, and the depletion layer is connected to the substrate. The bottom extension makes the substrate bear part of the withstand voltage after depletion, which increases the vertical withstand voltage length of the device, and with the decrease of the substrate concentration, the vertical withstand voltage further increases, and the breakdown voltage of the SOI device is changed from the vertical and lateral voltages The smaller one determines that in order to increase the breakdown voltage of conventional SOI devices, the withstand voltage layer is completely depleted, and the doping of the drift region must be low. The vertical withstand voltage is determined by the thickness of the drift region and the buried oxide layer under the drain end surface. The thickness of the drift region from the source to the drain is the same, and the surface electric field is not optimized. Although some SOI devices break the limitation of the vertical withstand voltage of conventional SOI, the surface electric field must satisfy the principle of RESURF, and the surface field will appear high at both ends. The middle low distribution shape makes the drift region of the second-type impurity device not fully optimized, and the limitations of RESURF itself limit the electric field modulation in the drift region, so that the electric field distribution in the drift region of the second-type impurity device cannot be improved, such as figure 1 As shown, a conventional SOI device includes a source, a drain, a first-type impurity substrate 1, a buried oxide layer 2, and a second-type impurity top-layer silicon layer 3, and the second-type impurity top-layer silicon layer 3 includes a first-type impurity Back gate contact region 7, source second-type impurity ohmic contact region 6, second-type impurity device drift region 5, and drain second-type impurity ohmic contact region 4, the first-type impurity substrate 1 is arranged on a horizontal plane , the buried oxide layer 2 is arranged on the first-type impurity substrate 1, the second-type impurity device drift region 5 is arranged on the buried oxide layer 2, and the buried oxide layer 2 connects the first-type impurity substrate 1 and the second-type impurity top layer The silicon layer 3 is electrically isolated, the first-type impurity back gate contact region 8 and the source second-type impurity ohmic contact region 7 are juxtaposed, and are arranged on the upper surface of the second-type impurity device drift region 5 and is close to the source. Drain second-type impurity ohmic contact region 4 is set on the upper surface of second-type impurity device drift region 5 near the drain, wherein the first-type impurity is p-type impurity or n-type impurity, and the second-type impurity is n-type impurity or p-type impurity

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