Embedded sram structure and chip

Abstract

An embedded Static random access memory (SRAM) chip includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is defined by a first X-pitch and a first Y-pitch, the X-pitch being longer than the Y-pitch. A plurality of logic transistors are formed outside of the first SRAM array, the plurality of logic transistors including at least first and second logic transistor having first and second gate pitches defined between their source and drain contacts. The second gate pitch is the minimum logic gate pitch for the plurality of logic transistors. The first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one. The invention can improve the SER reliability, improve static noise margin and transistor match.

Description

technical field [0001] The present invention generally relates to a semiconductor device, and also relates to a memory lattice, and further relates to the structure and layout design of the static random access memory lattice. Background technique [0002] Static Random Access Memory (SRAM) is often used in integrated circuits. Embedded SRAM is widely used in high-speed communication, image processing and single-chip system (System On Chip, SOC) and other fields. The advantage of the SRAM lattice is that it can retain data without refreshing. Generally, an SRAM cell includes two pass-gate transistors through which one bit of data can be written into or read out of the SRAM. The type of SRAM lattice mentioned above is called a single-port SRAM lattice. Another type of SRAM cell is called a dual port SRAM cell, which includes four pass-gate transistors. Figure 1A , Figure 1B and Figure 1C They are: a six-transistor single-port SRAM lattice circuit, an eight-transistor ...

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Problems solved by technology

However, reducing the gate length in order to reduce the transistor pitch will affect the controllability and data stability of the device

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