Framework of high speed and low power consumption serial communication data receiving interface

Abstract

The invention relates to a framework of a high speed and low power consumption serial communication data receiving interface, which discards the arrangement of a multi-channel oversampling and arbitration circuit. Through utilizing the technology of combining single-channel sampling asynchronization and multiple-clock automatic synchronization, an original clock frequency signal CLK is extracted from input data, and content data are pre-sampled; and after the pre-sampling data and a system clock are synchronized, a clock CLK1 is fed back and adjusted to a single-channel sampling module so that a result of precisely sampling the content data is completely synchronous to a target clock CLK2, thereby realizing the combination of clock domain asynchronization and synchronization and improving the efficiency. Under the condition of the similar realization area of an ASIC (Application Specific Integrated Circuit), the power consumption of realizing a physical layer (PHY) is reduced by more than 70% and exceeds the international level achieved by the traditional realization framework, thereby reducing the interference of a high speed signal on other circuits inside an ASIC chip, lowering the requirements for the layout and the wiring of a module inside the chip, reducing the energy consumption and also lowering the production cost.

Description

technical field [0001] The invention relates to an integrated circuit design and implementation, in particular to a high-speed and low-power serial communication data receiving interface architecture. Background technique [0002] With the rapid development of modern digital communication technology, interconnection technology with a rate above 5Gbit / s is being more and more widely used, such as high-speed backplane of communication system, interconnection between backplanes of communication system, local area network, very short distance between communication equipment Optical interconnection (VSR), SATA high-speed transmission standard, Express PCI2.0 and USB3.0 protocol, etc. These interconnection methods often require the support of high-speed, low-power, and cheap integrated circuits to achieve higher performance-cost ratios. [0003] The above-mentioned high-speed digital communication systems generally transmit data in a serial manner, but do not provide a dedicated ...

AI Technical Summary

Problems solved by technology

[0009] For example, the general-purpose USB2.0 physical layer (PHY) implemented using such an architecture consumes about 60mA of current at high speed, which is not a big problem for general applications, but it is a huge heat source for integrated image sensors such as CIS. It will seriously affect the image quality captured by the image sensor

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