Register circuit realizing grouping addressing and read write control method for register files

Abstract

The invention discloses a register circuit realizing a grouping addressing and read write control method for register files, which comprises a write back data generating module, a write address and control signal generating module, two register RAMs, two read address and control signal generating modules and two operand generating modules, wherein the first register comprises a register group of RAM0-RAM3, the second register comprises a register group of RAM4-RAM7, and the size of each register group is one quarter of the register file; the output of the write back data generating module is respectively connected with 32-bit data input of each register group; the output of the write address and control signal generating module is respectively connected with the write control input of each register group; the register group of RAM0-RAM3 outputs a 128-bit first source operand through the first operand generating module; and the register group of RAM4-RAM7 outputs a 128-bit second source operand through the second operand generating module.

Description

technical field [0001] The invention relates to a group addressing, reading and writing control method and circuit realization structure of a floating-point register file in a 32-bit RISC processor. Background technique [0002] The reduced instruction set (RISC) processor generally adopts a register-based computing mode, and its source operand comes from a register or an immediate value, and the execution result is generally written back to the register. Based on such structural characteristics, in order to support simultaneous access of multiple operands, the registers of the RISC processor must provide at least two read ports and one write port. In specific processor design, there are two typical design ideas: 1) full custom design: document "A Small, Fast and Low-PowerRegister File by Bit-Partitioning" (Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11 2005)) and "The Alpha 21264 Microprocessor (IEEE MICRO, Vol.19 (2)) in...

AI Technical Summary

Problems solved by technology

This calculation mode, in which multiple registers jointly provide an operand, requires multiple reads and writes to the register file. In the design of high-performance microprocessors, this multi-register for preparing operands and writing back results The access cycle has a greater impact on the performance of the processor

[0005] How to unify the register access time of different operand formats is a problem that must be solved in the design of high-performance processors, especially in the design of floating-point coprocessors. After searching relevant literature and patents, no solution to this problem has been found.

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